Module idma_axi_write
Implementing the AXI4 write task in the iDMA transport layer.
Parameters
StrbWidth: int unsigned
Stobe width
MaskInvalidData: bit
Mask invalid data on the manager interface
byte_t: type
Byte type
data_t: type
Data type
strb_t: type
Offset type
write_req_t: type
AXI 4 Request channel type
write_rsp_t: type
AXI 4 Response channel type
w_dp_req_t: type
w_dp_req_t type:
w_dp_rsp_t: type
w_dp_rsp_t type:
aw_chan_t: type
AXI 4 AW channel type
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
w_dp_req_i: input w_dp_req_t
Write datapath request
w_dp_valid_i: input logic
Write datapath request valid
w_dp_ready_o: output logic
Write datapath request ready
dp_poison_i: input logic
Datapath poison signal
w_dp_rsp_o: output w_dp_rsp_t
Write datapath response
w_dp_valid_o: output logic
Write datapath response valid
w_dp_ready_i: input logic
Write datapath response valid
aw_req_i: input aw_chan_t
Write meta request
aw_valid_i: input logic
Write meta request valid
aw_ready_o: output logic
Write meta request ready
write_req_o: output write_req_t
AXI4+ATOP write manager port request
write_rsp_i: input write_rsp_t
AXI4+ATOP write manager port response
buffer_out_i: input byte_t [StrbWidth-1:0]
Data from buffer
buffer_out_valid_i: input strb_t
Valid from buffer
buffer_out_ready_o: output strb_t
Ready to buffer