Module idma_backend_synth_rw_axi_rw_axis
Synthesis wrapper for the iDMA backend. Unpacks all the interfaces to simple logic vectors
Parameters
DataWidth: int unsigned
Data width
AddrWidth: int unsigned
Address width
UserWidth: int unsigned
AXI user width
AxiIdWidth: int unsigned
AXI ID width
NumAxInFlight: int unsigned
Number of transaction that can be in-flight concurrently
BufferDepth: int unsigned
The depth of the internal reorder buffer:
-
‘2’: minimal possible configuration
-
‘3’: efficiently handle misaligned transfers (recommended)
TFLenWidth: int unsigned
With of a transfer: max transfer size is 2**TFLenWidth bytes
MemSysDepth: int unsigned
The depth of the memory system the backend is attached to
CombinedShifter: bit
Should both data shifts be done before the dataflow element?
If this is enabled, then the data inserted into the dataflow element
will no longer be word aligned, but only a single shifter is needed
MaskInvalidData: bit
Mask invalid data on the manager interface
RAWCouplingAvail: bit
Should the R-AW coupling hardware be present? (recommended)
HardwareLegalizer: bit
Should hardware legalization be present? (recommended)
If not, software legalization is required to ensure the transfers are
AXI4-conformal
RejectZeroTransfers: bit
Reject zero-length transfers
ErrorHandling: bit
Should the error handler be present?
StrbWidth: int unsigned
Strobe Width (do not override!)
OffsetWidth: int unsigned
Offset Width (do not override!)
addr_t: type
Address type (do not override!)
data_t: type
Data type (do not override!)
strb_t: type
Strobe type (do not override!)
user_t: type
User type (do not override!)
id_t: type
ID type (do not override!)
tf_len_t: type
Transfer length type (do not override!)
offset_t: type
Offset type (do not override!)
ErrorCap: idma_pkg::error_cap_e
Define the error handling capability
axi_aw_chan_width: int unsigned
axi_ar_chan_width: int unsigned
axis_t_chan_width: int unsigned
Ports
clk_i: input logic
rst_ni: input logic
test_i: input logic
req_valid_i: input logic
req_ready_o: output logic
req_length_i: input tf_len_t
req_src_addr_i: input addr_t
req_dst_addr_i: input addr_t
req_src_protocol_i: input idma_pkg::protocol_e
req_dst_protocol_i: input idma_pkg::protocol_e
req_axi_id_i: input id_t
req_src_burst_i: input axi_pkg::burst_t
req_src_cache_i: input axi_pkg::cache_t
req_src_lock_i: input logic
req_src_prot_i: input axi_pkg::prot_t
req_src_qos_i: input axi_pkg::qos_t
req_src_region_i: input axi_pkg::region_t
req_dst_burst_i: input axi_pkg::burst_t
req_dst_cache_i: input axi_pkg::cache_t
req_dst_lock_i: input logic
req_dst_prot_i: input axi_pkg::prot_t
req_dst_qos_i: input axi_pkg::qos_t
req_dst_region_i: input axi_pkg::region_t
req_decouple_aw_i: input logic
req_decouple_rw_i: input logic
req_src_max_llen_i: input logic [2:0]
req_dst_max_llen_i: input logic [2:0]
req_src_reduce_len_i: input logic
req_dst_reduce_len_i: input logic
req_last_i: input logic
rsp_valid_o: output logic
rsp_ready_i: input logic
rsp_cause_o: output axi_pkg::resp_t
rsp_err_type_o: output idma_pkg::err_type_t
rsp_burst_addr_o: output addr_t
rsp_error_o: output logic
rsp_last_o: output logic
eh_req_valid_i: input logic
eh_req_ready_o: output logic
eh_req_i: input idma_pkg::idma_eh_req_t
axi_ar_id_o: output id_t
axi_ar_addr_o: output addr_t
axi_ar_len_o: output axi_pkg::len_t
axi_ar_size_o: output axi_pkg::size_t
axi_ar_burst_o: output axi_pkg::burst_t
axi_ar_lock_o: output logic
axi_ar_cache_o: output axi_pkg::cache_t
axi_ar_prot_o: output axi_pkg::prot_t
axi_ar_qos_o: output axi_pkg::qos_t
axi_ar_region_o: output axi_pkg::region_t
axi_ar_user_o: output user_t
axi_ar_valid_o: output logic
axi_ar_ready_i: input logic
axi_r_id_i: input id_t
axi_r_data_i: input data_t
axi_r_resp_i: input axi_pkg::resp_t
axi_r_last_i: input logic
axi_r_user_i: input user_t
axi_r_valid_i: input logic
axi_r_ready_o: output logic
axis_read_data_i: input data_t
axis_read_strb_i: input strb_t
axis_read_keep_i: input strb_t
axis_read_last_i: input logic
axis_read_id_i: input id_t
axis_read_dest_i: input id_t
axis_read_user_i: input user_t
axis_read_tvalid_i: input logic
axis_read_tready_o: output logic
axi_aw_id_o: output id_t
axi_aw_addr_o: output addr_t
axi_aw_len_o: output axi_pkg::len_t
axi_aw_size_o: output axi_pkg::size_t
axi_aw_burst_o: output axi_pkg::burst_t
axi_aw_lock_o: output logic
axi_aw_cache_o: output axi_pkg::cache_t
axi_aw_prot_o: output axi_pkg::prot_t
axi_aw_qos_o: output axi_pkg::qos_t
axi_aw_region_o: output axi_pkg::region_t
axi_aw_atop_o: output axi_pkg::atop_t
axi_aw_user_o: output user_t
axi_aw_valid_o: output logic
axi_aw_ready_i: input logic
axi_w_data_o: output data_t
axi_w_strb_o: output strb_t
axi_w_last_o: output logic
axi_w_user_o: output user_t
axi_w_valid_o: output logic
axi_w_ready_i: input logic
axi_b_id_i: input id_t
axi_b_resp_i: input axi_pkg::resp_t
axi_b_user_i: input user_t
axi_b_valid_i: input logic
axi_b_ready_o: output logic
axis_write_data_o: output data_t
axis_write_strb_o: output strb_t
axis_write_keep_o: output strb_t
axis_write_last_o: output logic
axis_write_id_o: output id_t
axis_write_dest_o: output id_t
axis_write_user_o: output user_t
axis_write_tvalid_o: output logic
axis_write_tready_i: input logic
idma_busy_o: output idma_pkg::idma_busy_t
Types
| axi_aw_chan_t | |
| axi_w_chan_t | |
| axi_b_chan_t | |
| axi_ar_chan_t | |
| axi_r_chan_t | |
| axi_req_t | |
| axi_rsp_t | |
| axis_t_chan_t | |
| axis_req_t | |
| axis_rsp_t | |
| options_t | Option struct: AXI4 id as well as AXI and backend options |
| idma_req_t | 1D iDMA request type: |
| err_payload_t | 1D iDMA response payload: |
| idma_rsp_t | 1D iDMA response type: |
| axi_read_ar_chan_padded_t | |
| axis_read_t_chan_padded_t | |
| read_meta_channel_t | |
| axi_write_aw_chan_padded_t | |
| axis_write_t_chan_padded_t | |
| write_meta_channel_t |