Module idma_error_handler

Handles AXI read and write error on the manager interface.

Currently two modes are supported:

Parameters

MetaFifoDepth: int unsigned

Number of active transfers in the data path as well as in the memory system

PrintFifoInfo: bit

Print the info of the FIFO configuration

idma_rsp_t: type

1D iDMA response type

idma_eh_req_t: type

Error handling request type

addr_t: type

Address type

r_dp_rsp_t: type

Read datapath response type

w_dp_rsp_t: type

Write datapath response type

Ports

clk_i: input logic

Clock

rst_ni: input logic

Asynchronous reset, active low

testmode_i: input logic

Testmode in

rsp_o: output idma_rsp_t

1D iDMA response

rsp_valid_o: output logic

1D iDMA response valid

rsp_ready_i: input logic

1D iDMA response ready

eh_i: input idma_eh_req_t

Error handling request

eh_valid_i: input logic

Error handling request valid

eh_ready_o: output logic

Error handling request ready

req_valid_i: input logic

1D iDMA request valid

req_ready_i: input logic

1D iDMA request ready

r_addr_i: input addr_t

The current read address (burst address) injected into the datapath

r_consume_i: input logic

The address is consumed by the datapath

w_addr_i: input addr_t

The current write address (burst address) injected into the datapath

w_consume_i: input logic

The address is consumed by the datapath

legalizer_flush_o: output logic

Invalidate the current burst transfer, stops emission of requests

legalizer_kill_o: output logic

Kill the active 1D transfer; reload a new transfer

dp_busy_i: input logic

The datapath is busy at the moment. This includes the read & write machines as well as the

buffer.

dp_poison_o: output logic

If the datapath has the ability to mask invalid data (MaskInvalidData set to True), this

flag masks the output during flushes to reduce toggling activities

r_dp_rsp_i: input r_dp_rsp_t

Read datapath response

r_dp_valid_i: input logic

Read datapath response valid

r_dp_ready_o: output logic

Read datapath response ready

w_dp_rsp_i: input w_dp_rsp_t

Write datapath response

w_dp_valid_i: input logic

Write datapath response valid

w_dp_ready_o: output logic

Write datapath response ready

w_last_burst_i: input logic

Write datapath currently works on last burst of a 1D transfer

w_super_last_i: input logic

The last flag which is assigned by the controlling unit

fsm_busy_o: output logic

Error handler is busy

cnt_busy_o: output logic

Types

num_outst_t

The number of outstanding 1D transfers in the datapath needs to be tracked with a simple

error_state_e

The state of the error handling FSM:

Signals

state_d: error_state_e

state_q: error_state_e

r_addr_head: addr_t

w_addr_head: addr_t

num_outst_d: num_outst_t

num_outst_q: num_outst_t