Module passthrough_stream_fifo
Stream FIFO that does not cut the timing path. When full; pushing data is allowed if in
the same cycle data is popped. Creates longer timing paths but can use buffer space more
efficiently.
Parameters
Depth: int unsigned
Depth can be arbitrary from 2 to 2**32
PrintInfo: bit
Print information when the simulation launches
SameCycleRW: bit
If the FIFO is full, allow reading and writing in the same cycle
type_t: type
Type of the FIFO
PointerWidth: int unsigned
Bit Width of the read and write pointers
One additional bit to detect overflows
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset active low
flush_i: input logic
Fifo flush
testmode_i: input logic
Bypass clock gate
data_i: input type_t
data to push into the FIFO
valid_i: input logic
input data valid
ready_o: output logic
FIFO is not full
data_o: output type_t
output data
valid_o: output logic
FIFO is not empty
ready_i: input logic
pop head from FIFO