Module idma_backend_r_obi_w_axi
The iDMA backend implements an arbitrary 1D copy engine
Parameters
DataWidth: int unsigned
Data width
AddrWidth: int unsigned
Address width
UserWidth: int unsigned
AXI user width
AxiIdWidth: int unsigned
AXI ID width
NumAxInFlight: int unsigned
Number of transaction that can be in-flight concurrently
BufferDepth: int unsigned
The depth of the internal reorder buffer:
-
‘2’: minimal possible configuration
-
‘3’: efficiently handle misaligned transfers (recommended)
TFLenWidth: int unsigned
With of a transfer: max transfer size is 2**TFLenWidth bytes
MemSysDepth: int unsigned
The depth of the memory system the backend is attached to
CombinedShifter: bit
Should both data shifts be done before the dataflow element?
If this is enabled, then the data inserted into the dataflow element
will no longer be word aligned, but only a single shifter is needed
RAWCouplingAvail: bit
Should the R-AW coupling hardware be present? (recommended)
MaskInvalidData: bit
Mask invalid data on the manager interface
HardwareLegalizer: bit
Should hardware legalization be present? (recommended)
If not, software legalization is required to ensure the transfers are
AXI4-conformal
RejectZeroTransfers: bit
Reject zero-length transfers
ErrorCap: idma_pkg::error_cap_e
Should the error handler be present?
PrintFifoInfo: bit
Print the info of the FIFO configuration
idma_req_t: type
1D iDMA request type
idma_rsp_t: type
iDMA response type
idma_eh_req_t: type
Error Handler request type
idma_busy_t: type
iDMA busy signal
axi_req_t: type
AXI4+ATOP Request and Response channel type
axi_rsp_t: type
obi_req_t: type
OBI Request and Response channel type
obi_rsp_t: type
read_meta_channel_t: type
Address Read Channel type
write_meta_channel_t: type
Address Write Channel type
StrbWidth: int unsigned
Strobe Width (do not override!)
OffsetWidth: int unsigned
Offset Width (do not override!)
MetaFifoDepth: int unsigned
The localparam MetaFifoDepth holds the maximum number of transfers that can be
in-flight under any circumstances.
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
testmode_i: input logic
Testmode in
idma_req_i: input idma_req_t
1D iDMA request
req_valid_i: input logic
1D iDMA request valid
req_ready_o: output logic
1D iDMA request ready
idma_rsp_o: output idma_rsp_t
iDMA response
rsp_valid_o: output logic
iDMA response valid
rsp_ready_i: input logic
iDMA response ready
idma_eh_req_i: input idma_eh_req_t
Error handler request
eh_req_valid_i: input logic
Error handler request valid
eh_req_ready_o: output logic
Error handler request ready
obi_read_req_o: output obi_req_t
OBI read request
obi_read_rsp_i: input obi_rsp_t
OBI read response
axi_write_req_o: output axi_req_t
AXI4+ATOP write request
axi_write_rsp_i: input axi_rsp_t
AXI4+ATOP write response
busy_o: output idma_busy_t
iDMA busy flags
Types
| addr_t | Address type |
| data_t | DAta type |
| strb_t | Strobe type |
| user_t | User type |
| id_t | ID type |
| offset_t | Offset type |
| tf_len_t | Transfer length type |
| r_dp_req_t | The datapath read request type holds all the information required to configure the read |
| r_dp_rsp_t | The datapath read response type provides feedback from the read part of the datapath: |
| w_dp_req_t | The datapath write request type holds all the information required to configure the write |
| w_dp_rsp_t | The datapath write response type provides feedback from the write part of the datapath: |
| idma_r_req_t | The iDMA read request bundles an |
| idma_w_req_t | The iDMA write request bundles an |
| idma_mut_tf_opt_t | The mutable transfer options type holds important information that is mutated by the |
| idma_mut_tf_t | The mutable transfer type holds important information that is mutated by the |