Module idma_desc64_ar_gen_prefetch
This module generates AR packets to fetch descriptors from memory
Parameters
DataWidth: int unsigned
AXI Data width
NSpeculation: int unsigned
How many descriptors may be prefetched
descriptor_t: type
Descriptor type. $bits(descriptor_t) must be a power of two
axi_ar_chan_t: type
AXI AR channel type
axi_id_t: type
AXI AR id type
usage_t: type
Type that can hold the usage information of the idma_req fifo
addr_t: type
AXI Address type
flush_t: type
Type that can hold how many descriptors to flush on the R channel.
Do not override.
DataWidthBytes: int unsigned
DescriptorSize: int unsigned
AxiSize: logic [2:0]
AxiLength: logic [7:0]
SpeculationWidth: int unsigned
SpeculationUsageWidth: int unsigned
Ports
clk_i: input logic
Clock
rst_ni: input logic
Reset
axi_ar_chan_o: output axi_ar_chan_t
AXI AR channel
axi_ar_chan_valid_o: output logic
AXI AR valid
axi_ar_chan_ready_i: input logic
AXI AR ready
axi_ar_id_i: input axi_id_t
AXI ID to use when requesting
queued_address_i: input addr_t
queued address to use when we reach the last in a chain
queued_address_valid_i: input logic
queued address valid
queued_address_ready_o: output logic
queued address ready
next_address_from_descriptor_i: input addr_t
next address as read from descriptor
next_address_from_descriptor_valid_i: input logic
next address valid
idma_req_available_slots_i: input usage_t
number of available slots in the idma request fifo
n_requests_to_flush_o: output flush_t
number of requests to flush on the R channel
n_requests_to_flush_valid_o: output logic
if asserted, flush n_requests_to_flush_o on the R channel
feedback_addr_o: output addr_t
address for feedback for the next request
feedback_addr_valid_o: output logic
feedback address valid
busy_o: output logic
whether the unit is busy
Types
| addr_spec_t |