Module idma_desc64_synth

synth wrapper

Parameters

`AddrWidth: int unsigned`

`DataWidth: int unsigned`

`AxiIdWidth: int unsigned`

`idma_req_t: type`

`idma_rsp_t: type`

`axi_rsp_t: type`

`axi_req_t: type`

`axi_ar_chan_t: type`

`axi_r_chan_t: type`

`reg_rsp_t: type`

`reg_req_t: type`

`InputFifoDepth: int unsigned`

`PendingFifoDepth: int unsigned`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`master_req_o: output axi_req_t`

`master_rsp_i: input axi_rsp_t`

`axi_ar_id_i: input logic [AxiIdWidth-1:0]`

`axi_aw_id_i: input logic [AxiIdWidth-1:0]`

`slave_req_i: input reg_req_t`

`slave_rsp_o: output reg_rsp_t`

`idma_req_o: output idma_req_t`

`idma_req_valid_o: output logic`

`idma_req_ready_i: input logic`

`idma_rsp_i: input idma_rsp_t`

`idma_rsp_valid_i: input logic`

`idma_rsp_ready_o: output logic`

`idma_busy_i: input logic`

`irq_o: output logic`