Module idma_desc64_top
This module serves as a descriptor-based frontend for the iDMA in the CVA6-core
Parameters
AddrWidth: int unsigned
Width of the addresses
DataWidth: int unsigned
Width of a data item on the AXI bus
AxiIdWidth: int unsigned
Width an AXI ID
idma_req_t: type
burst request type. See the documentation of the idma backend for details
idma_rsp_t: type
burst response type. See the documentation of the idma backend for details
reg_rsp_t: type
regbus interface types. Use the REG_BUS_TYPEDEF macros to define the types
or see the idma backend documentation for more details
reg_req_t: type
axi_rsp_t: type
AXI interface types used for fetching descriptors.
Use the AXI_TYPEDEF_ALL macros to define the types
axi_req_t: type
axi_ar_chan_t: type
axi_r_chan_t: type
InputFifoDepth: int unsigned
Specifies the depth of the fifo behind the descriptor address register
PendingFifoDepth: int unsigned
Specifies the buffer size of the fifo that tracks requests submitted to the backend
BackendDepth: int unsigned
How many requests the backend might have at the same time in its buffers.
Usually, NumAxInFlight + BufferDepth
NSpeculation: int unsigned
Specifies how many descriptors may be fetched speculatively
MaxAWWPending: int unsigned
Specifies how many unsent AWs/Ws are allowed
PendingFifoDepthBits: int unsigned
Ports
clk_i: input logic
clock
rst_ni: input logic
reset
master_req_o: output axi_req_t
axi interface used for fetching descriptors
master pair
master request
master_rsp_i: input axi_rsp_t
master response
axi_ar_id_i: input logic [AxiIdWidth-1:0]
ID to be used by the read channel
axi_aw_id_i: input logic [AxiIdWidth-1:0]
ID to be used by the write channel
slave_req_i: input reg_req_t
regbus interface
slave pair
The slave interface exposes two registers: One address register to
write a descriptor address to process and a status register that
exposes whether the DMA is busy on bit 0 and whether FIFOs are full
on bit 1.
master request
slave_rsp_o: output reg_rsp_t
master response
idma_req_o: output idma_req_t
backend interface
burst request submission
burst request data. See iDMA backend documentation for fields
idma_req_valid_o: output logic
valid signal for the backend data submission
idma_req_ready_i: input logic
ready signal for the backend data submission
idma_rsp_i: input idma_rsp_t
status information from the backend
idma_rsp_valid_i: input logic
valid signal for the backend response
idma_rsp_ready_o: output logic
ready signal for the backend response
idma_busy_i: input logic
whether the backend is currently busy
irq_o: output logic
Event: irq
Types
| addr_t | |
| descriptor_t | Descriptor layout |
| flush_t |