Module idma_legalizer_rw_axi_rw_axis
Legalizes a generic 1D transfer according to the rules given by the
used protocol.
Parameters
CombinedShifter: bit
Should both data shifts be done before the dataflow element?
If this is enabled, then the data inserted into the dataflow element
will no longer be word aligned, but only a single shifter is needed
DataWidth: int unsigned
Data width
AddrWidth: int unsigned
Address width
idma_req_t: type
1D iDMA request type:
-
length: the length of the transfer in bytes -
*_addr: the source / target byte addresses of the transfer -
opt: the options field
idma_r_req_t: type
Read request type
idma_w_req_t: type
Write request type
idma_mut_tf_t: type
Mutable transfer type
idma_mut_tf_opt_t: type
Mutable options type
StrbWidth: int unsigned
Stobe width
OffsetWidth: int unsigned
Offset width
PageSize: int unsigned
The size of a page in byte
PageAddrWidth: int unsigned
The width of page offset byte addresses
Ports
clk_i: input logic
Clock
rst_ni: input logic
Asynchronous reset, active low
req_i: input idma_req_t
1D request
valid_i: input logic
1D request valid
ready_o: output logic
1D request ready
r_req_o: output idma_r_req_t
Read request; contains datapath and meta information
r_valid_o: output logic
Read request valid
r_ready_i: input logic
Read request ready
w_req_o: output idma_w_req_t
Write request; contains datapath and meta information
w_valid_o: output logic
Write request valid
w_ready_i: input logic
Write request ready
flush_i: input logic
Invalidate the current burst transfer, stops emission of requests
kill_i: input logic
Kill the active 1D transfer; reload a new transfer
r_busy_o: output logic
Read machine of the legalizer is busy
w_busy_o: output logic
Write machine of the legalizer is busy
Types
| offset_t | Offset type |
| addr_t | Address type |
| page_addr_t | Page address type |
| page_len_t | Page length type |