Module prim_subreg

Parameters

DW: int

SWACCESS:

RESVAL: logic [DW-1:0]

Ports

clk_i: input

rst_ni: input

we: input

wd: input [DW-1:0]

de: input

d: input [DW-1:0]

qe: output logic

q: output logic [DW-1:0]

qs: output logic [DW-1:0]