Module idma_nd_midend

ND midend for the iDMA. This module takes an n-dimensional transfer and splits it into

individual 1d transfers handed to the backend.

Parameters

NumDim: int unsigned

Number of dimensions. This has to be at least two as the first dimension is already

handled by the backend itself

addr_t: type

Address type

idma_req_t: type

1D iDMA request type

idma_rsp_t: type

iDMA response type

idma_nd_req_t: type

ND iDMA request type

RepWidths: logic [NumDim-1:0][31:0]

The width of the counters holding the number of repetitions.

StrideSelWidth: int unsigned

How many bits are required to index the counters

RepWidth: int unsigned

Ports

clk_i: input logic

Clock

rst_ni: input logic

Asynchronous reset, active low

nd_req_i: input idma_nd_req_t

ND iDMA request

nd_req_valid_i: input logic

ND iDMA request valid

nd_req_ready_o: output logic

ND iDMA request ready

nd_rsp_o: output idma_rsp_t

ND iDMA response

nd_rsp_valid_o: output logic

ND iDMA response valid

nd_rsp_ready_i: input logic

ND iDMA response ready

burst_req_o: output idma_req_t

1D iDMA request

burst_req_valid_o: output logic

1D iDMA request valid

burst_req_ready_i: input logic

1D iDMA request ready

burst_rsp_i: input idma_rsp_t

iDMA 1D response

burst_rsp_valid_i: input logic

iDMA 1D response valid

burst_rsp_ready_o: output logic

iDMA 1D response ready

busy_o: output logic

the backend is busy

Signals

src_addr_d: addr_t

src_addr_q: addr_t

dst_addr_d: addr_t

dst_addr_q: addr_t