/github/workspace/src/BasicMathFunctions/dot_prod/kernels/plp_dot_prod_q16s_rv32im.c

Functions

	Name
void	plp_dot_prod_q16s_rv32im(const int16_t restrict pSrcA, const int16_t restrict pSrcB, uint32_t blockSize, uint32_t deciPoint, int32_t *restrict pRes) Scalar dot product of 16-bit fixed point vectors kernel for RV32IM extension.

Functions Documentation

function plp_dot_prod_q16s_rv32im

void plp_dot_prod_q16s_rv32im(
    const int16_t *__restrict__ pSrcA,
    const int16_t *__restrict__ pSrcB,
    uint32_t blockSize,
    uint32_t deciPoint,
    int32_t *__restrict__ pRes
)

Scalar dot product of 16-bit fixed point vectors kernel for RV32IM extension.

Parameters:

• pSrcA points to the first input vector [16 bit]
• pSrcB points to the second input vector [16 bit]
• blockSize number of samples in each vector
• deciPoint decimal point for right shift
• pRes output result returned here [32 bit]

Return: none

Par: Exploiting SIMD instructions

When the ISA supports, the 16 bit values are packed two by two into 32 bit vectors and then the two dot products are performed simultaneously on 32 bit vectors, with 32 bit accumulator. RV32IM doesn't support SIMD. For SIMD, check out other ISA extensions (e.g. XPULPV2).

Source code

/* =====================================================================
 * Project:      PULP DSP Library
 * Title:        plp_dot_prod_q16s_rv32im.c
 * Description:  16-bit fixed point scalar dot product kernel for RV32IM
 *
 * $Date:        28. May 2019
 * $Revision:    V0
 *
 * Target Processor: PULP cores
 * ===================================================================== */
/*
 * Copyright (C) 2019 ETH Zurich and University of Bologna.
 *
 * Author: Xiaying Wang, ETH Zurich
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * Notice: project inspired by ARM CMSIS DSP and parts of source code
 * ported and adopted for RISC-V PULP platform from ARM CMSIS DSP
 * released under Copyright (C) 2010-2019 ARM Limited or its affiliates
 * with Apache-2.0.
 */

#include "plp_math.h"

void plp_dot_prod_q16s_rv32im(const int16_t *__restrict__ pSrcA,
                              const int16_t *__restrict__ pSrcB,
                              uint32_t blockSize,
                              uint32_t deciPoint,
                              int32_t *__restrict__ pRes) {
    uint32_t blkCnt; /* Loop counter */
    int32_t sum = 0; /* Temporary return variable */

    int32_t bias = 1 << (deciPoint - 1);

#if defined(PLP_MATH_LOOPUNROLL)

    for (blkCnt = 0; blkCnt < (blockSize >> 2); blkCnt++) {
        int32_t tmp;
        tmp = (*pSrcA++) * (*pSrcB++);
        tmp += (*pSrcA++) * (*pSrcB++);
        tmp += (*pSrcA++) * (*pSrcB++);
        tmp += (*pSrcA++) * (*pSrcB++);
        sum += (tmp + bias) >> deciPoint;
    }

    for (blkCnt = 0; blkCnt < (blockSize % 4U); blkCnt++) {
        sum += (((*pSrcA++) * (*pSrcB++)) + bias) >> deciPoint;
    }

#else // PLP_MATH_LOOPUNROLL

    for (blkCnt = 0; blkCnt < blockSize; blkCnt++) {
        sum += (((*pSrcA++) * (*pSrcB++)) + bias) >> deciPoint;
    }

#endif // PLP_MATH_LOOPUNROLL

    *pRes = sum;
}

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Updated on 2023-03-01 at 16:16:32 +0000