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snRuntime/vendor/riscv-opcodes/encoding.h

Defines

Name
MSTATUS_UIE
MSTATUS_SIE
MSTATUS_HIE
MSTATUS_MIE
MSTATUS_UPIE
MSTATUS_SPIE
MSTATUS_UBE
MSTATUS_MPIE
MSTATUS_SPP
MSTATUS_VS
MSTATUS_MPP
MSTATUS_FS
MSTATUS_XS
MSTATUS_MPRV
MSTATUS_SUM
MSTATUS_MXR
MSTATUS_TVM
MSTATUS_TW
MSTATUS_TSR
MSTATUS32_SD
MSTATUS_UXL
MSTATUS_SXL
MSTATUS_SBE
MSTATUS_MBE
MSTATUS_GVA
MSTATUS_MPV
MSTATUS64_SD
MSTATUSH_SBE
MSTATUSH_MBE
SSTATUS_UIE
SSTATUS_SIE
SSTATUS_UPIE
SSTATUS_SPIE
SSTATUS_UBE
SSTATUS_SPP
SSTATUS_VS
SSTATUS_FS
SSTATUS_XS
SSTATUS_SUM
SSTATUS_MXR
SSTATUS32_SD
SSTATUS_UXL
SSTATUS64_SD
SSTATUS_VS_MASK
HSTATUS_VSXL
HSTATUS_VTSR
HSTATUS_VTW
HSTATUS_VTVM
HSTATUS_VGEIN
HSTATUS_HU
HSTATUS_SPVP
HSTATUS_SPV
HSTATUS_GVA
HSTATUS_VSBE
USTATUS_UIE
USTATUS_UPIE
DCSR_XDEBUGVER
DCSR_NDRESET
DCSR_FULLRESET
DCSR_EBREAKM
DCSR_EBREAKH
DCSR_EBREAKS
DCSR_EBREAKU
DCSR_STOPCYCLE
DCSR_STOPTIME
DCSR_CAUSE
DCSR_DEBUGINT
DCSR_HALT
DCSR_STEP
DCSR_PRV
DCSR_CAUSE_NONE
DCSR_CAUSE_SWBP
DCSR_CAUSE_HWBP
DCSR_CAUSE_DEBUGINT
DCSR_CAUSE_STEP
DCSR_CAUSE_HALT
DCSR_CAUSE_GROUP
MCONTROL_TYPE(xlen)
MCONTROL_DMODE(xlen)
MCONTROL_MASKMAX(xlen)
MCONTROL_SELECT
MCONTROL_TIMING
MCONTROL_ACTION
MCONTROL_CHAIN
MCONTROL_MATCH
MCONTROL_M
MCONTROL_H
MCONTROL_S
MCONTROL_U
MCONTROL_EXECUTE
MCONTROL_STORE
MCONTROL_LOAD
MCONTROL_TYPE_NONE
MCONTROL_TYPE_MATCH
MCONTROL_ACTION_DEBUG_EXCEPTION
MCONTROL_ACTION_DEBUG_MODE
MCONTROL_ACTION_TRACE_START
MCONTROL_ACTION_TRACE_STOP
MCONTROL_ACTION_TRACE_EMIT
MCONTROL_MATCH_EQUAL
MCONTROL_MATCH_NAPOT
MCONTROL_MATCH_GE
MCONTROL_MATCH_LT
MCONTROL_MATCH_MASK_LOW
MCONTROL_MATCH_MASK_HIGH
MIP_USIP
MIP_SSIP
MIP_VSSIP
MIP_MSIP
MIP_UTIP
MIP_STIP
MIP_VSTIP
MIP_MTIP
MIP_UEIP
MIP_SEIP
MIP_VSEIP
MIP_MEIP
MIP_SGEIP
SIP_SCIP
MIP_MCIP
MIE_SSIE
MIE_HSIE
MIE_MSIE
MIE_STIE
MIE_HTIE
MIE_MTIE
MIE_SEIE
MIE_HEIE
MIE_MEIE
MIE_SCIE
MIE_MCIE
MCAUSE_INTERRUPT
MIP_S_MASK
MIP_VS_MASK
MIP_HS_MASK
MIDELEG_FORCED_MASK
SIP_SSIP
SIP_STIP
PRV_U
PRV_S
PRV_M
PRV_HS
SATP32_MODE
SATP32_ASID
SATP32_PPN
SATP64_MODE
SATP64_ASID
SATP64_PPN
SATP_MODE_OFF
SATP_MODE_SV32
SATP_MODE_SV39
SATP_MODE_SV48
SATP_MODE_SV57
SATP_MODE_SV64
HGATP32_MODE
HGATP32_VMID
HGATP32_PPN
HGATP64_MODE
HGATP64_VMID
HGATP64_PPN
HGATP_MODE_OFF
HGATP_MODE_SV32X4
HGATP_MODE_SV39X4
HGATP_MODE_SV48X4
PMP_R
PMP_W
PMP_X
PMP_A
PMP_L
PMP_SHIFT
PMP_TOR
PMP_NA4
PMP_NAPOT
IRQ_U_SOFT
IRQ_S_SOFT
IRQ_VS_SOFT
IRQ_M_SOFT
IRQ_U_TIMER
IRQ_S_TIMER
IRQ_VS_TIMER
IRQ_M_TIMER
IRQ_U_EXT
IRQ_S_EXT
IRQ_VS_EXT
IRQ_M_EXT
IRQ_S_GEXT
IRQ_COP
IRQ_HOST
IRQ_M_CLUSTER
IRQ_S_CLUSTER
PTE_V
PTE_R
PTE_W
PTE_X
PTE_U
PTE_G
PTE_A
PTE_D
PTE_SOFT
PTE_RSVD
PTE_PBMT
PTE_N
PTE_ATTR
PTE_PPN_SHIFT
PTE_TABLE(PTE)

Macros Documentation

define MSTATUS_UIE

#define MSTATUS_UIE 0x00000001

define MSTATUS_SIE

#define MSTATUS_SIE 0x00000002

define MSTATUS_HIE

#define MSTATUS_HIE 0x00000004

define MSTATUS_MIE

#define MSTATUS_MIE 0x00000008

define MSTATUS_UPIE

#define MSTATUS_UPIE 0x00000010

define MSTATUS_SPIE

#define MSTATUS_SPIE 0x00000020

define MSTATUS_UBE

#define MSTATUS_UBE 0x00000040

define MSTATUS_MPIE

#define MSTATUS_MPIE 0x00000080

define MSTATUS_SPP

#define MSTATUS_SPP 0x00000100

define MSTATUS_VS

#define MSTATUS_VS 0x00000600

define MSTATUS_MPP

#define MSTATUS_MPP 0x00001800

define MSTATUS_FS

#define MSTATUS_FS 0x00006000

define MSTATUS_XS

#define MSTATUS_XS 0x00018000

define MSTATUS_MPRV

#define MSTATUS_MPRV 0x00020000

define MSTATUS_SUM

#define MSTATUS_SUM 0x00040000

define MSTATUS_MXR

#define MSTATUS_MXR 0x00080000

define MSTATUS_TVM

#define MSTATUS_TVM 0x00100000

define MSTATUS_TW

#define MSTATUS_TW 0x00200000

define MSTATUS_TSR

#define MSTATUS_TSR 0x00400000

define MSTATUS32_SD

#define MSTATUS32_SD 0x80000000

define MSTATUS_UXL

#define MSTATUS_UXL 0x0000000300000000

define MSTATUS_SXL

#define MSTATUS_SXL 0x0000000C00000000

define MSTATUS_SBE

#define MSTATUS_SBE 0x0000001000000000

define MSTATUS_MBE

#define MSTATUS_MBE 0x0000002000000000

define MSTATUS_GVA

#define MSTATUS_GVA 0x0000004000000000

define MSTATUS_MPV

#define MSTATUS_MPV 0x0000008000000000

define MSTATUS64_SD

#define MSTATUS64_SD 0x8000000000000000

define MSTATUSH_SBE

#define MSTATUSH_SBE 0x00000010

define MSTATUSH_MBE

#define MSTATUSH_MBE 0x00000020

define SSTATUS_UIE

#define SSTATUS_UIE 0x00000001

define SSTATUS_SIE

#define SSTATUS_SIE 0x00000002

define SSTATUS_UPIE

#define SSTATUS_UPIE 0x00000010

define SSTATUS_SPIE

#define SSTATUS_SPIE 0x00000020

define SSTATUS_UBE

#define SSTATUS_UBE 0x00000040

define SSTATUS_SPP

#define SSTATUS_SPP 0x00000100

define SSTATUS_VS

#define SSTATUS_VS 0x00000600

define SSTATUS_FS

#define SSTATUS_FS 0x00006000

define SSTATUS_XS

#define SSTATUS_XS 0x00018000

define SSTATUS_SUM

#define SSTATUS_SUM 0x00040000

define SSTATUS_MXR

#define SSTATUS_MXR 0x00080000

define SSTATUS32_SD

#define SSTATUS32_SD 0x80000000

define SSTATUS_UXL

#define SSTATUS_UXL 0x0000000300000000

define SSTATUS64_SD

#define SSTATUS64_SD 0x8000000000000000

define SSTATUS_VS_MASK

#define SSTATUS_VS_MASK     (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_SUM | \
     SSTATUS_MXR | SSTATUS_UXL)

define HSTATUS_VSXL

#define HSTATUS_VSXL 0x300000000

define HSTATUS_VTSR

#define HSTATUS_VTSR 0x00400000

define HSTATUS_VTW

#define HSTATUS_VTW 0x00200000

define HSTATUS_VTVM

#define HSTATUS_VTVM 0x00100000

define HSTATUS_VGEIN

#define HSTATUS_VGEIN 0x0003f000

define HSTATUS_HU

#define HSTATUS_HU 0x00000200

define HSTATUS_SPVP

#define HSTATUS_SPVP 0x00000100

define HSTATUS_SPV

#define HSTATUS_SPV 0x00000080

define HSTATUS_GVA

#define HSTATUS_GVA 0x00000040

define HSTATUS_VSBE

#define HSTATUS_VSBE 0x00000020

define USTATUS_UIE

#define USTATUS_UIE 0x00000001

define USTATUS_UPIE

#define USTATUS_UPIE 0x00000010

define DCSR_XDEBUGVER

#define DCSR_XDEBUGVER (3U << 30)

define DCSR_NDRESET

#define DCSR_NDRESET (1 << 29)

define DCSR_FULLRESET

#define DCSR_FULLRESET (1 << 28)

define DCSR_EBREAKM

#define DCSR_EBREAKM (1 << 15)

define DCSR_EBREAKH

#define DCSR_EBREAKH (1 << 14)

define DCSR_EBREAKS

#define DCSR_EBREAKS (1 << 13)

define DCSR_EBREAKU

#define DCSR_EBREAKU (1 << 12)

define DCSR_STOPCYCLE

#define DCSR_STOPCYCLE (1 << 10)

define DCSR_STOPTIME

#define DCSR_STOPTIME (1 << 9)

define DCSR_CAUSE

#define DCSR_CAUSE (7 << 6)

define DCSR_DEBUGINT

#define DCSR_DEBUGINT (1 << 5)

define DCSR_HALT

#define DCSR_HALT (1 << 3)

define DCSR_STEP

#define DCSR_STEP (1 << 2)

define DCSR_PRV

#define DCSR_PRV (3 << 0)

define DCSR_CAUSE_NONE

#define DCSR_CAUSE_NONE 0

define DCSR_CAUSE_SWBP

#define DCSR_CAUSE_SWBP 1

define DCSR_CAUSE_HWBP

#define DCSR_CAUSE_HWBP 2

define DCSR_CAUSE_DEBUGINT

#define DCSR_CAUSE_DEBUGINT 3

define DCSR_CAUSE_STEP

#define DCSR_CAUSE_STEP 4

define DCSR_CAUSE_HALT

#define DCSR_CAUSE_HALT 5

define DCSR_CAUSE_GROUP

#define DCSR_CAUSE_GROUP 6

define MCONTROL_TYPE

#define MCONTROL_TYPE(
    xlen
)
(0xfULL << ((xlen)-4))

define MCONTROL_DMODE

#define MCONTROL_DMODE(
    xlen
)
(1ULL << ((xlen)-5))

define MCONTROL_MASKMAX

#define MCONTROL_MASKMAX(
    xlen
)
(0x3fULL << ((xlen)-11))

define MCONTROL_SELECT

#define MCONTROL_SELECT (1 << 19)

define MCONTROL_TIMING

#define MCONTROL_TIMING (1 << 18)

define MCONTROL_ACTION

#define MCONTROL_ACTION (0x3f << 12)

define MCONTROL_CHAIN

#define MCONTROL_CHAIN (1 << 11)

define MCONTROL_MATCH

#define MCONTROL_MATCH (0xf << 7)

define MCONTROL_M

#define MCONTROL_M (1 << 6)

define MCONTROL_H

#define MCONTROL_H (1 << 5)

define MCONTROL_S

#define MCONTROL_S (1 << 4)

define MCONTROL_U

#define MCONTROL_U (1 << 3)

define MCONTROL_EXECUTE

#define MCONTROL_EXECUTE (1 << 2)

define MCONTROL_STORE

#define MCONTROL_STORE (1 << 1)

define MCONTROL_LOAD

#define MCONTROL_LOAD (1 << 0)

define MCONTROL_TYPE_NONE

#define MCONTROL_TYPE_NONE 0

define MCONTROL_TYPE_MATCH

#define MCONTROL_TYPE_MATCH 2

define MCONTROL_ACTION_DEBUG_EXCEPTION

#define MCONTROL_ACTION_DEBUG_EXCEPTION 0

define MCONTROL_ACTION_DEBUG_MODE

#define MCONTROL_ACTION_DEBUG_MODE 1

define MCONTROL_ACTION_TRACE_START

#define MCONTROL_ACTION_TRACE_START 2

define MCONTROL_ACTION_TRACE_STOP

#define MCONTROL_ACTION_TRACE_STOP 3

define MCONTROL_ACTION_TRACE_EMIT

#define MCONTROL_ACTION_TRACE_EMIT 4

define MCONTROL_MATCH_EQUAL

#define MCONTROL_MATCH_EQUAL 0

define MCONTROL_MATCH_NAPOT

#define MCONTROL_MATCH_NAPOT 1

define MCONTROL_MATCH_GE

#define MCONTROL_MATCH_GE 2

define MCONTROL_MATCH_LT

#define MCONTROL_MATCH_LT 3

define MCONTROL_MATCH_MASK_LOW

#define MCONTROL_MATCH_MASK_LOW 4

define MCONTROL_MATCH_MASK_HIGH

#define MCONTROL_MATCH_MASK_HIGH 5

define MIP_USIP

#define MIP_USIP (1 << IRQ_U_SOFT)

define MIP_SSIP

#define MIP_SSIP (1 << IRQ_S_SOFT)

define MIP_VSSIP

#define MIP_VSSIP (1 << IRQ_VS_SOFT)

define MIP_MSIP

#define MIP_MSIP (1 << IRQ_M_SOFT)

define MIP_UTIP

#define MIP_UTIP (1 << IRQ_U_TIMER)

define MIP_STIP

#define MIP_STIP (1 << IRQ_S_TIMER)

define MIP_VSTIP

#define MIP_VSTIP (1 << IRQ_VS_TIMER)

define MIP_MTIP

#define MIP_MTIP (1 << IRQ_M_TIMER)

define MIP_UEIP

#define MIP_UEIP (1 << IRQ_U_EXT)

define MIP_SEIP

#define MIP_SEIP (1 << IRQ_S_EXT)

define MIP_VSEIP

#define MIP_VSEIP (1 << IRQ_VS_EXT)

define MIP_MEIP

#define MIP_MEIP (1 << IRQ_M_EXT)

define MIP_SGEIP

#define MIP_SGEIP (1 << IRQ_S_GEXT)

define SIP_SCIP

#define SIP_SCIP (1 << IRQ_S_CLUSTER)

define MIP_MCIP

#define MIP_MCIP (1 << IRQ_M_CLUSTER)

define MIE_SSIE

#define MIE_SSIE (1 << IRQ_S_SOFT)

define MIE_HSIE

#define MIE_HSIE (1 << IRQ_H_SOFT)

define MIE_MSIE

#define MIE_MSIE (1 << IRQ_M_SOFT)

define MIE_STIE

#define MIE_STIE (1 << IRQ_S_TIMER)

define MIE_HTIE

#define MIE_HTIE (1 << IRQ_H_TIMER)

define MIE_MTIE

#define MIE_MTIE (1 << IRQ_M_TIMER)

define MIE_SEIE

#define MIE_SEIE (1 << IRQ_S_EXT)

define MIE_HEIE

#define MIE_HEIE (1 << IRQ_H_EXT)

define MIE_MEIE

#define MIE_MEIE (1 << IRQ_M_EXT)

define MIE_SCIE

#define MIE_SCIE (1 << IRQ_S_CLUSTER)

define MIE_MCIE

#define MIE_MCIE (1 << IRQ_M_CLUSTER)

define MCAUSE_INTERRUPT

#define MCAUSE_INTERRUPT 0x80000000

define MIP_S_MASK

#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP)

define MIP_VS_MASK

#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)

define MIP_HS_MASK

#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP)

define MIDELEG_FORCED_MASK

#define MIDELEG_FORCED_MASK MIP_HS_MASK

define SIP_SSIP

#define SIP_SSIP MIP_SSIP

define SIP_STIP

#define SIP_STIP MIP_STIP

define PRV_U

#define PRV_U 0

define PRV_S

#define PRV_S 1

define PRV_M

#define PRV_M 3

define PRV_HS

#define PRV_HS (PRV_S + 1)

define SATP32_MODE

#define SATP32_MODE 0x80000000

define SATP32_ASID

#define SATP32_ASID 0x7FC00000

define SATP32_PPN

#define SATP32_PPN 0x003FFFFF

define SATP64_MODE

#define SATP64_MODE 0xF000000000000000

define SATP64_ASID

#define SATP64_ASID 0x0FFFF00000000000

define SATP64_PPN

#define SATP64_PPN 0x00000FFFFFFFFFFF

define SATP_MODE_OFF

#define SATP_MODE_OFF 0

define SATP_MODE_SV32

#define SATP_MODE_SV32 1

define SATP_MODE_SV39

#define SATP_MODE_SV39 8

define SATP_MODE_SV48

#define SATP_MODE_SV48 9

define SATP_MODE_SV57

#define SATP_MODE_SV57 10

define SATP_MODE_SV64

#define SATP_MODE_SV64 11

define HGATP32_MODE

#define HGATP32_MODE 0x80000000

define HGATP32_VMID

#define HGATP32_VMID 0x1FC00000

define HGATP32_PPN

#define HGATP32_PPN 0x003FFFFF

define HGATP64_MODE

#define HGATP64_MODE 0xF000000000000000

define HGATP64_VMID

#define HGATP64_VMID 0x03FFF00000000000

define HGATP64_PPN

#define HGATP64_PPN 0x00000FFFFFFFFFFF

define HGATP_MODE_OFF

#define HGATP_MODE_OFF 0

define HGATP_MODE_SV32X4

#define HGATP_MODE_SV32X4 1

define HGATP_MODE_SV39X4

#define HGATP_MODE_SV39X4 8

define HGATP_MODE_SV48X4

#define HGATP_MODE_SV48X4 9

define PMP_R

#define PMP_R 0x01

define PMP_W

#define PMP_W 0x02

define PMP_X

#define PMP_X 0x04

define PMP_A

#define PMP_A 0x18

define PMP_L

#define PMP_L 0x80

define PMP_SHIFT

#define PMP_SHIFT 2

define PMP_TOR

#define PMP_TOR 0x08

define PMP_NA4

#define PMP_NA4 0x10

define PMP_NAPOT

#define PMP_NAPOT 0x18

define IRQ_U_SOFT

#define IRQ_U_SOFT 0

define IRQ_S_SOFT

#define IRQ_S_SOFT 1

define IRQ_VS_SOFT

#define IRQ_VS_SOFT 2

define IRQ_M_SOFT

#define IRQ_M_SOFT 3

define IRQ_U_TIMER

#define IRQ_U_TIMER 4

define IRQ_S_TIMER

#define IRQ_S_TIMER 5

define IRQ_VS_TIMER

#define IRQ_VS_TIMER 6

define IRQ_M_TIMER

#define IRQ_M_TIMER 7

define IRQ_U_EXT

#define IRQ_U_EXT 8

define IRQ_S_EXT

#define IRQ_S_EXT 9

define IRQ_VS_EXT

#define IRQ_VS_EXT 10

define IRQ_M_EXT

#define IRQ_M_EXT 11

define IRQ_S_GEXT

#define IRQ_S_GEXT 12

define IRQ_COP

#define IRQ_COP 12

define IRQ_HOST

#define IRQ_HOST 13

define IRQ_M_CLUSTER

#define IRQ_M_CLUSTER 19

define IRQ_S_CLUSTER

#define IRQ_S_CLUSTER 17

define PTE_V

#define PTE_V 0x001                 /* Valid */

define PTE_R

#define PTE_R 0x002                 /* Read */

define PTE_W

#define PTE_W 0x004                 /* Write */

define PTE_X

#define PTE_X 0x008                 /* Execute */

define PTE_U

#define PTE_U 0x010                 /* User */

define PTE_G

#define PTE_G 0x020                 /* Global */

define PTE_A

#define PTE_A 0x040                 /* Accessed */

define PTE_D

#define PTE_D 0x080                 /* Dirty */

define PTE_SOFT

#define PTE_SOFT 0x300              /* Reserved for Software */

define PTE_RSVD

#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */

define PTE_PBMT

#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */

define PTE_N

#define PTE_N 0x8000000000000000    /* Svnapot: NAPOT translation contiguity */

define PTE_ATTR

#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */

define PTE_PPN_SHIFT

#define PTE_PPN_SHIFT 10

define PTE_TABLE

#define PTE_TABLE(
    PTE
)
(((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

Source code

/* See LICENSE for license details. */

#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H

#ifdef __cplusplus
extern "C" {
#endif

#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_UBE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_VS 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_SUM 0x00040000
#define MSTATUS_MXR 0x00080000
#define MSTATUS_TVM 0x00100000
#define MSTATUS_TW 0x00200000
#define MSTATUS_TSR 0x00400000
#define MSTATUS32_SD 0x80000000
#define MSTATUS_UXL 0x0000000300000000
#define MSTATUS_SXL 0x0000000C00000000
#define MSTATUS_SBE 0x0000001000000000
#define MSTATUS_MBE 0x0000002000000000
#define MSTATUS_GVA 0x0000004000000000
#define MSTATUS_MPV 0x0000008000000000
#define MSTATUS64_SD 0x8000000000000000

#define MSTATUSH_SBE 0x00000010
#define MSTATUSH_MBE 0x00000020

#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_UBE 0x00000040
#define SSTATUS_SPP 0x00000100
#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_SUM 0x00040000
#define SSTATUS_MXR 0x00080000
#define SSTATUS32_SD 0x80000000
#define SSTATUS_UXL 0x0000000300000000
#define SSTATUS64_SD 0x8000000000000000

#define SSTATUS_VS_MASK                                                    \
    (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_SUM | \
     SSTATUS_MXR | SSTATUS_UXL)

#define HSTATUS_VSXL 0x300000000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_VTW 0x00200000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VGEIN 0x0003f000
#define HSTATUS_HU 0x00000200
#define HSTATUS_SPVP 0x00000100
#define HSTATUS_SPV 0x00000080
#define HSTATUS_GVA 0x00000040
#define HSTATUS_VSBE 0x00000020

#define USTATUS_UIE 0x00000001
#define USTATUS_UPIE 0x00000010

#define DCSR_XDEBUGVER (3U << 30)
#define DCSR_NDRESET (1 << 29)
#define DCSR_FULLRESET (1 << 28)
#define DCSR_EBREAKM (1 << 15)
#define DCSR_EBREAKH (1 << 14)
#define DCSR_EBREAKS (1 << 13)
#define DCSR_EBREAKU (1 << 12)
#define DCSR_STOPCYCLE (1 << 10)
#define DCSR_STOPTIME (1 << 9)
#define DCSR_CAUSE (7 << 6)
#define DCSR_DEBUGINT (1 << 5)
#define DCSR_HALT (1 << 3)
#define DCSR_STEP (1 << 2)
#define DCSR_PRV (3 << 0)

#define DCSR_CAUSE_NONE 0
#define DCSR_CAUSE_SWBP 1
#define DCSR_CAUSE_HWBP 2
#define DCSR_CAUSE_DEBUGINT 3
#define DCSR_CAUSE_STEP 4
#define DCSR_CAUSE_HALT 5
#define DCSR_CAUSE_GROUP 6

#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4))
#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))

#define MCONTROL_SELECT (1 << 19)
#define MCONTROL_TIMING (1 << 18)
#define MCONTROL_ACTION (0x3f << 12)
#define MCONTROL_CHAIN (1 << 11)
#define MCONTROL_MATCH (0xf << 7)
#define MCONTROL_M (1 << 6)
#define MCONTROL_H (1 << 5)
#define MCONTROL_S (1 << 4)
#define MCONTROL_U (1 << 3)
#define MCONTROL_EXECUTE (1 << 2)
#define MCONTROL_STORE (1 << 1)
#define MCONTROL_LOAD (1 << 0)

#define MCONTROL_TYPE_NONE 0
#define MCONTROL_TYPE_MATCH 2

#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
#define MCONTROL_ACTION_DEBUG_MODE 1
#define MCONTROL_ACTION_TRACE_START 2
#define MCONTROL_ACTION_TRACE_STOP 3
#define MCONTROL_ACTION_TRACE_EMIT 4

#define MCONTROL_MATCH_EQUAL 0
#define MCONTROL_MATCH_NAPOT 1
#define MCONTROL_MATCH_GE 2
#define MCONTROL_MATCH_LT 3
#define MCONTROL_MATCH_MASK_LOW 4
#define MCONTROL_MATCH_MASK_HIGH 5

#define MIP_USIP (1 << IRQ_U_SOFT)
#define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_VSSIP (1 << IRQ_VS_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT)
#define MIP_UTIP (1 << IRQ_U_TIMER)
#define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_VSTIP (1 << IRQ_VS_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER)
#define MIP_UEIP (1 << IRQ_U_EXT)
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_VSEIP (1 << IRQ_VS_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
#define MIP_SGEIP (1 << IRQ_S_GEXT)
#define SIP_SCIP (1 << IRQ_S_CLUSTER)
#define MIP_MCIP (1 << IRQ_M_CLUSTER)

#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_HSIE (1 << IRQ_H_SOFT)
#define MIE_MSIE (1 << IRQ_M_SOFT)
#define MIE_STIE (1 << IRQ_S_TIMER)
#define MIE_HTIE (1 << IRQ_H_TIMER)
#define MIE_MTIE (1 << IRQ_M_TIMER)
#define MIE_SEIE (1 << IRQ_S_EXT)
#define MIE_HEIE (1 << IRQ_H_EXT)
#define MIE_MEIE (1 << IRQ_M_EXT)
#define MIE_SCIE (1 << IRQ_S_CLUSTER)
#define MIE_MCIE (1 << IRQ_M_CLUSTER)

#define MCAUSE_INTERRUPT 0x80000000

#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP)

#define MIDELEG_FORCED_MASK MIP_HS_MASK

#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP

#define PRV_U 0
#define PRV_S 1
#define PRV_M 3

#define PRV_HS (PRV_S + 1)

#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7FC00000
#define SATP32_PPN 0x003FFFFF
#define SATP64_MODE 0xF000000000000000
#define SATP64_ASID 0x0FFFF00000000000
#define SATP64_PPN 0x00000FFFFFFFFFFF

#define SATP_MODE_OFF 0
#define SATP_MODE_SV32 1
#define SATP_MODE_SV39 8
#define SATP_MODE_SV48 9
#define SATP_MODE_SV57 10
#define SATP_MODE_SV64 11

#define HGATP32_MODE 0x80000000
#define HGATP32_VMID 0x1FC00000
#define HGATP32_PPN 0x003FFFFF

#define HGATP64_MODE 0xF000000000000000
#define HGATP64_VMID 0x03FFF00000000000
#define HGATP64_PPN 0x00000FFFFFFFFFFF

#define HGATP_MODE_OFF 0
#define HGATP_MODE_SV32X4 1
#define HGATP_MODE_SV39X4 8
#define HGATP_MODE_SV48X4 9

#define PMP_R 0x01
#define PMP_W 0x02
#define PMP_X 0x04
#define PMP_A 0x18
#define PMP_L 0x80
#define PMP_SHIFT 2

#define PMP_TOR 0x08
#define PMP_NA4 0x10
#define PMP_NAPOT 0x18

#define IRQ_U_SOFT 0
#define IRQ_S_SOFT 1
#define IRQ_VS_SOFT 2
#define IRQ_M_SOFT 3
#define IRQ_U_TIMER 4
#define IRQ_S_TIMER 5
#define IRQ_VS_TIMER 6
#define IRQ_M_TIMER 7
#define IRQ_U_EXT 8
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
#define IRQ_COP 12
#define IRQ_HOST 13
#define IRQ_M_CLUSTER 19
#define IRQ_S_CLUSTER 17

/* page table entry (PTE) fields */
#define PTE_V 0x001                 /* Valid */
#define PTE_R 0x002                 /* Read */
#define PTE_W 0x004                 /* Write */
#define PTE_X 0x008                 /* Execute */
#define PTE_U 0x010                 /* User */
#define PTE_G 0x020                 /* Global */
#define PTE_A 0x040                 /* Accessed */
#define PTE_D 0x080                 /* Dirty */
#define PTE_SOFT 0x300              /* Reserved for Software */
#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */
#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */
#define PTE_N 0x8000000000000000    /* Svnapot: NAPOT translation contiguity */
#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */

#define PTE_PPN_SHIFT 10

#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

#ifdef __riscv

#if __riscv_xlen == 64
#define MSTATUS_SD MSTATUS64_SD
#define SSTATUS_SD SSTATUS64_SD
#define RISCV_PGLEVEL_BITS 9
#define SATP_MODE SATP64_MODE
#else
#define MSTATUS_SD MSTATUS32_SD
#define SSTATUS_SD SSTATUS32_SD
#define RISCV_PGLEVEL_BITS 10
#define SATP_MODE SATP32_MODE
#endif
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)

#ifndef __ASSEMBLER__

#ifdef __GNUC__

#define read_csr(reg)                                 \
    ({                                                \
        unsigned long __tmp;                          \
        asm volatile("csrr %0, " #reg : "=r"(__tmp)); \
        __tmp;                                        \
    })

#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); })

#define swap_csr(reg, val)                                                \
    ({                                                                    \
        unsigned long __tmp;                                              \
        asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
        __tmp;                                                            \
    })

#define set_csr(reg, bit)                                                 \
    ({                                                                    \
        unsigned long __tmp;                                              \
        asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
        __tmp;                                                            \
    })

#define clear_csr(reg, bit)                                               \
    ({                                                                    \
        unsigned long __tmp;                                              \
        asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
        __tmp;                                                            \
    })

#define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle)
#define rdinstret() read_csr(instret)

#endif  // __GNUC__

#endif  // __ASSEMBLER__

#endif  // __riscv

#ifdef __cplusplus
}
#endif

#endif  // RISCV_CSR_ENCODING_H

Updated on 2023-06-19 at 09:43:56 +0000