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7#define FCMP_FUNCT5 0b10100
8#define FCVT_D_INT_FUNCT5 0b11010
10#define OP_FP_FMT_D 0b01
12#define FLT_FUNCT3 0b001
14#define FCVT_D_WU_RS2 0b00001
16#define FLT_D_SSR(rd, rs1, rs2) \
17 R_TYPE_ENCODE((FCMP_FUNCT5 << 2 | OP_FP_FMT_D), rs2, rs1, FLT_FUNCT3, rd, \
20#define FCVT_D_WU_SSR(rd, rs1) \
21 R_TYPE_ENCODE((FCVT_D_INT_FUNCT5 << 2 | OP_FP_FMT_D), FCVT_D_WU_RS2, rs1, \
22 0b000, rd, OP_CUSTOM1)
29inline void snrt_ssr_flt(
double lval,
double rval) {
30 register double reg_lval
asm(
"fa0") = lval;
31 register double reg_rval
asm(
"fa1") = rval;
34 asm volatile(
".word %[insn]\n"
36 : [ insn ]
"i"(FLT_D_SSR(2, 10, 11)),
"f"(lval),
"f"(rval));
43inline double snrt_ssr_fcvt() {
44 register double reg_result
asm(
"fa0");
47 asm volatile(
".word %[insn]\n"
49 : [ insn ]
"i"(FCVT_D_WU_SSR(10, 0)));