riscv.h

// Copyright 2023 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#include "riscv_decls.h"
 
#pragma once
 
#include "../../deps/riscv-opcodes/encoding.h"
 
inline void snrt_wfi() { asm volatile("wfi"); }
 
inline void snrt_nop() { asm volatile("nop" : : :); }
 
inline uint32_t snrt_mcycle() {
    uint32_t register r;
    asm volatile("csrr %0, mcycle" : "=r"(r) : : "memory");
    return r;
}
 
inline void snrt_interrupt_enable(uint32_t irq) { set_csr(mie, 1 << irq); }
 
inline void snrt_interrupt_disable(uint32_t irq) { clear_csr(mie, 1 << irq); }
 
inline void snrt_interrupt_global_enable(void) {
    set_csr(mstatus, MSTATUS_MIE);  // set M global interrupt enable
}
inline void snrt_interrupt_global_disable(void) {
    clear_csr(mstatus, MSTATUS_MIE);
}