Ara

Introduction:

  • Introduction

SoC:

  • ara_soc: Top-Level Dummy SoC for Ara
  • ara_system: Integration of CVA6 and Ara

Ara:

  • ara: Top-Level Vector Unit
  • ara_dispatcher — Vector Instruction Decoder and Issuer
  • segment_sequencer - Split segment memory operations into multiple micro-ops
  • ara_sequencer — Instruction sequencer and macro dependency check

SLDU

  • sldu — Ara’s slide unit, for permutations, shuffles, and slides

MASKU

  • masku — Ara’s mask unit, for mask bits dispatch, mask operations, bits handling

VLSU

  • vlsu - Vector Load/Store Unit
  • addrgen: Ara Vector Address Generation Unit
  • vldu: Ara’s Vector Load Unit
  • vstu: Ara Vector Store Unit

Lane

  • lane — Ara’s lane, hosting a vector register file slice and functional units
  • lane_sequencer — Set up the in-lane operations
  • vrf — Ara’s Vector Register File (VRF)
  • operand_requester Module Documentation
  • operand_queues_stage — Instantiate the in-lane operand queues
  • operand_queue — Buffer between the VRF and the functional units
  • vector_fus_stage Module Documentation
  • valu - Instantiate the in-lane SIMD ALU (unpipelined)
  • simd_alu - Ara’s in-lane SIMD ALU (simd_alu)
  • fixed_p_rounding - Set up fixed-point arithmetic rounding information
  • vmfpu — Instantiate in-lane SIMD FPU, SIMD multiplier, and SIMD divider (pipelined or multi-cycle)
  • simd_mul — Ara’s in-lane SIMD multiplier
  • simd_div — Ara’s in-lane SIMD divider
Ara
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