Module axi_id_remap
Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port.
This module is designed to remap an overly wide, sparsely used ID space to a narrower, densely
used ID space. This scenario occurs, for example, when an AXI master has wide ID ports but
effectively only uses a (not necessarily contiguous) subset of IDs.
This module retains the independence of IDs. That is, if two transactions have different IDs at
the slave port of this module, they are guaranteed to have different IDs at the master port of
this module. This implies a lower bound on the [width of IDs on the master
port](#parameter.AxiMstPortIdWidth). If you require narrower master port IDs and can forgo ID
independence, use axi_id_serialize instead.
Internally, a table is used for remapping IDs.
Parameters
AxiSlvPortIdWidth: int unsigned
ID width of the AXI4+ATOP slave port.
AxiSlvPortMaxUniqIds: int unsigned
Maximum number of different IDs that can be in flight at the slave port. Reads and writes are
counted separately (except for ATOPs, which count as both read and write).
It is legal for upstream to have transactions with more unique IDs than the maximum given by
this parameter in flight, but a transaction exceeding the maximum will be stalled until all
transactions of another ID complete.
The maximum value of this parameter is 2**AxiSlvPortIdWidth.
AxiMaxTxnsPerId: int unsigned
Maximum number of in-flight transactions with the same ID.
It is legal for upstream to have more transactions than the maximum given by this parameter in
flight for any ID, but a transaction exceeding the maximum will be stalled until another
transaction with the same ID completes.
AxiMstPortIdWidth: int unsigned
ID width of the AXI4+ATOP master port.
The minimum value of this parameter is the ceiled binary logarithm of AxiSlvPortMaxUniqIds,
because IDs at the master port must be wide enough to represent IDs up to
AxiSlvPortMaxUniqIds-1.
If master IDs are wider than the minimum, they are extended by prepending zeros.
slv_req_t: type
Request struct type of the AXI4+ATOP slave port.
The width of all IDs in this struct must match AxiSlvPortIdWidth.
slv_resp_t: type
Response struct type of the AXI4+ATOP slave port.
The width of all IDs in this struct must match AxiSlvPortIdWidth.
mst_req_t: type
Request struct type of the AXI4+ATOP master port
The width of all IDs in this struct must match AxiMstPortIdWidth.
mst_resp_t: type
Response struct type of the AXI4+ATOP master port
The width of all IDs in this struct must match AxiMstPortIdWidth.
IdxWidth: int unsigned
ZeroWidth:
Ports
clk_i: input logic
Rising-edge clock of all ports
rst_ni: input logic
Asynchronous reset, active low
slv_req_i: input slv_req_t
Slave port request
slv_resp_o: output slv_resp_t
Slave port response
mst_req_o: output mst_req_t
Master port request
mst_resp_i: input mst_resp_t
Master port response
Types
| field_t | |
| id_inp_t | |
| idx_t |