Module axi_id_serialize
Reduce AXI IDs by serializing transactions when necessary.
This module is designed to remap a wide ID space to an arbitrarily narrow ID space. If
necessary, this module maps two different IDs at its slave port to the same ID at its master
port, thereby constraining the order of those transactions and in this sense serializing them.
If the independence of IDs needs to be retained at the cost of a wider ID space at the master
port, use axi_id_remap instead.
This module contains one axi_serializer per master port ID (given by
the AxiMstPortMaxUniqIds parameter).
Parameters
AxiSlvPortIdWidth: int unsigned
ID width of the AXI4+ATOP slave port
AxiSlvPortMaxTxns: int unsigned
Maximum number of transactions that can be in flight at the slave port. Reads and writes are
counted separately (except for ATOPs, which count as both read and write).
AxiMstPortIdWidth: int unsigned
ID width of the AXI4+ATOP master port
AxiMstPortMaxUniqIds: int unsigned
Maximum number of different IDs that can be in flight at the master port. Reads and writes
are counted separately (except for ATOPs, which count as both read and write).
The maximum value of this parameter is 2**AxiMstPortIdWidth.
AxiMstPortMaxTxnsPerId: int unsigned
Maximum number of in-flight transactions with the same ID at the master port.
AxiAddrWidth: int unsigned
Address width of both AXI4+ATOP ports
AxiDataWidth: int unsigned
Data width of both AXI4+ATOP ports
AxiUserWidth: int unsigned
User width of both AXI4+ATOP ports
AtopSupport: bit
Enable support for AXI4+ATOP atomics
slv_req_t: type
Request struct type of the AXI4+ATOP slave port
slv_resp_t: type
Response struct type of the AXI4+ATOP slave port
mst_req_t: type
Request struct type of the AXI4+ATOP master port
mst_resp_t: type
Response struct type of the AXI4+ATOP master port
MstIdBaseOffset: int unsigned
A custom offset (modulo AxiMstPortMaxUniqIds, ignored for input IDs remapped through
IdMap) for the assigned output IDs.
IdMapNumEntries: int unsigned
Explicit input-output ID map. If an input ID id does not appear in this mapping (default),
it is simply mapped to the output ID id % AxiMstPortMaxUniqIds. If id appears in more
than one entry, it is matched to the last matching entry’s output ID.
Number of Entries in the explicit ID map (default: None)
IdMap: int unsigned
Explicit ID map; index [0] in each entry is the input ID to match, index [1] the output ID.
SelectWidth: int unsigned
Number of bits of the slave port ID that determine the mapping to the master port ID
MuxIdWidth: int unsigned
ID width after the multiplexer
SlvIdMap: slv_id_map_t
Input-to-output ID map used
Ports
clk_i: input logic
Rising-edge clock of both ports
rst_ni: input logic
Asynchronous reset, active low
slv_req_i: input slv_req_t
Slave port request
slv_resp_o: output slv_resp_t
Slave port response
mst_req_o: output mst_req_t
Master port request
mst_resp_i: input mst_resp_t
Master port response
Types
| select_t | Slice of slave port IDs that determines the master port ID |
| ser_id_t | ID after serializer (i.e., with a constant value of zero) |
| mux_id_t | ID after the multiplexer |
| slv_id_t | ID at the slave port |
| mst_id_t | ID at the master port |
| addr_t | Address in any AXI channel |
| data_t | Data in any AXI channel |
| strb_t | Strobe in any AXI channel |
| user_t | User signal in any AXI channel |
| w_t | W channel at any interface |
| slv_aw_t | AW channel at slave port |
| slv_b_t | B channel at slave port |
| slv_ar_t | AR channel at slave port |
| slv_r_t | R channel at slave port |
| ser_aw_t | AW channel after serializer |
| ser_b_t | B channel after serializer |
| ser_ar_t | AR channel after serializer |
| ser_r_t | R channel after serializer |
| ser_req_t | AXI Requests from serializer |
| ser_resp_t | AXI responses to serializer |
| mux_aw_t | AW channel after the multiplexer |
| mux_b_t | B channel after the multiplexer |
| mux_ar_t | AR channel after the multiplexer |
| mux_r_t | R channel after the multiplexer |
| mux_req_t | AXI requests from the multiplexer |
| mux_resp_t | AXI responses to the multiplexer |
| mst_aw_t | AW channel at master port |
| mst_b_t | B channel at master port |
| mst_ar_t | AR channel at master port |
| mst_r_t | R channel at master port |
| slv_id_map_t | Type for slave ID map |