Module axi_id_remap_intf

Interface variant of axi_id_remap.

See the documentation of the main module for the definition of ports and parameters.

Parameters

`AXI_SLV_PORT_ID_WIDTH: int unsigned`

`AXI_SLV_PORT_MAX_UNIQ_IDS: int unsigned`

`AXI_MAX_TXNS_PER_ID: int unsigned`

`AXI_MST_PORT_ID_WIDTH: int unsigned`

`AXI_ADDR_WIDTH: int unsigned`

`AXI_DATA_WIDTH: int unsigned`

`AXI_USER_WIDTH: int unsigned`

Ports

`clk_i: input logic`

`rst_ni: input logic`

`slv: AXI_BUS.Slave`

`mst: AXI_BUS.Master`

Types

slv_id_t
mst_id_t
axi_addr_t
axi_data_t
axi_strb_t
axi_user_t
slv_aw_chan_t
slv_w_chan_t
slv_b_chan_t
slv_ar_chan_t
slv_r_chan_t
slv_req_t
slv_resp_t
mst_aw_chan_t
mst_w_chan_t
mst_b_chan_t
mst_ar_chan_t
mst_r_chan_t
mst_req_t
mst_resp_t

Signals

`slv_req: slv_req_t`

`slv_resp: slv_resp_t`

`mst_req: mst_req_t`

`mst_resp: mst_resp_t`