Module axi_lite_regs_intf
Interface variant of axi_lite_regs.
See the documentation of the main module for the definition of ports and parameters.
Parameters
byte_t: type
REG_NUM_BYTES: int unsigned
AXI_ADDR_WIDTH: int unsigned
AXI_DATA_WIDTH: int unsigned
PRIV_PROT_ONLY: bit
SECU_PROT_ONLY: bit
AXI_READ_ONLY: logic [REG_NUM_BYTES-1:0]
REG_RST_VAL: byte_t [REG_NUM_BYTES-1:0]
Ports
clk_i: input logic
rst_ni: input logic
slv: AXI_LITE.Slave
wr_active_o: output logic [REG_NUM_BYTES-1:0]
rd_active_o: output logic [REG_NUM_BYTES-1:0]
reg_d_i: input byte_t [REG_NUM_BYTES-1:0]
reg_load_i: input logic [REG_NUM_BYTES-1:0]
reg_q_o: output byte_t [REG_NUM_BYTES-1:0]
Types
| addr_t | |
| data_t | |
| strb_t | |
| aw_chan_lite_t | |
| w_chan_lite_t | |
| b_chan_lite_t | |
| ar_chan_lite_t | |
| r_chan_lite_t | |
| req_lite_t | |
| resp_lite_t |