[INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][OpenROAD] Running scripts/03_cts.tcl [13:38 UTC] OpenROAD 26Q3-2443-g50432012f [13:38 UTC] Features included (+) or not (-): +GPU +GUI +Python [13:38 UTC] This program is licensed under the BSD-3 license. See the LICENSE file for details. [13:38 UTC] Components of this program may be licensed under more restrictive licenses which must be honored. [13:38 UTC] Setting up project croc [13:38 UTC] - Netlist: ../yosys/out/croc_yosys.v [13:38 UTC] - Project: croc [13:38 UTC] - Top design: croc_chip [13:38 UTC] - Report directory: reports [13:38 UTC] - Save directory: save [13:38 UTC] - Output directory: out [13:38 UTC] Init standard cells [13:38 UTC] Init IO cells [13:38 UTC] Init SRAM macros [13:38 UTC] Init tech-lef [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/ez130_cmos5l_tech.lef, created 15 layers, 52 vias [13:38 UTC] Init cell-lef [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/ez130_8t.lef, created 220 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/sg13cmos5l_io.lef, created 22 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/bondpad5l_70x70.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_256x64_c2_bm_bist.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_2048x64_c2_bm_bist.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_1024x64_c2_bm_bist.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_512x64_c2_bm_bist.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_256x48_c2_bm_bist.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_64x64_c2_bm_bist.lef, created 1 library cells [13:38 UTC] [INFO ODB-0227] LEF file: ../technology/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef, created 1 library cells [13:38 UTC] Loading checkpoint 02_croc.placed [13:38 UTC] Loading from ZIP file: save/02_croc.placed.zip [13:38 UTC] ############################################################################### [13:38 UTC] # Stage 03: CLOCK TREE SYNTHESIS [13:38 UTC] ############################################################################### [13:38 UTC] Repair clock inverters [13:38 UTC] Clock Tree Synthesis [13:38 UTC] [INFO CTS-0050] Root buffer is BUFX24. [13:38 UTC] [INFO CTS-0051] Sink buffer is BUFX24. [13:38 UTC] [INFO CTS-0052] The following clock buffers will be used for CTS: [13:38 UTC] BUFX8 [13:38 UTC] BUFX12 [13:38 UTC] BUFX16 [13:38 UTC] BUFX24 [13:38 UTC] [INFO CTS-0049] Characterization buffer is BUFX24. [13:39 UTC] [INFO CTS-0007] Net "clk_i" found for clock "clk_sys". [13:39 UTC] [INFO CTS-0116] Special net "clk_i" skipped. [13:39 UTC] [INFO CTS-0011] Clock net "soc_clk_i" for macros has 2 sinks. [13:39 UTC] [INFO CTS-0011] Clock net "soc_clk_i_regs" for registers has 1222 sinks. [13:39 UTC] [INFO CTS-0007] Net "jtag_tck_i" found for clock "clk_jtg". [13:39 UTC] [INFO CTS-0116] Special net "jtag_tck_i" skipped. [13:39 UTC] [INFO CTS-0011] Clock net "soc_jtag_tck_i" for macros has 1 sinks. [13:39 UTC] [INFO CTS-0011] Clock net "soc_jtag_tck_i_regs" for registers has 149 sinks. [13:39 UTC] [WARNING CTS-0041] Net "i_croc_soc\/i_croc\/i_dmi_jtag\/i_dmi_jtag_tap.tck_n" has 1 sinks. Skipping... [13:39 UTC] [INFO CTS-0007] Net "ref_clk_i" found for clock "clk_rtc". [13:39 UTC] [INFO CTS-0116] Special net "ref_clk_i" skipped. [13:39 UTC] [WARNING CTS-0041] Net "soc_ref_clk_i" has 1 sinks. Skipping... [13:39 UTC] [INFO CTS-0008] TritonCTS found 4 clock nets. [13:39 UTC] [INFO CTS-0097] Characterization used 4 buffer(s) types. [13:39 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:39 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_clk_i. [13:39 UTC] [INFO CTS-0028] Total number of sinks: 2. [13:39 UTC] [INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 833.3 um. [13:39 UTC] [INFO CTS-0030] Number of static layers: 0. [13:39 UTC] [INFO CTS-0020] Wire segment unit: 16800 dbu (16 um). [13:39 UTC] [INFO CTS-0023] Original sink region: [(483850, 1441750), (1420770, 1441750)]. [13:39 UTC] [INFO CTS-0024] Normalized sink region: [(28.8006, 85.8185), (84.5696, 85.8185)]. [13:39 UTC] [INFO CTS-0025] Width: 55.7690. [13:39 UTC] [INFO CTS-0026] Height: 0.0000. [13:39 UTC] Level 1 [13:39 UTC] Direction: Horizontal [13:39 UTC] Sinks per sub-region: 1 [13:39 UTC] Sub-region size: 27.8845 X 0.0000 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 14. [13:39 UTC] [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (3350.871 um) and max number of sinks is 15. [13:39 UTC] [INFO CTS-0035] Number of sinks covered: 2. [13:39 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:39 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_clk_i_regs. [13:39 UTC] [INFO CTS-0028] Total number of sinks: 1222. [13:39 UTC] [INFO CTS-0060] Register sinks will be clustered in groups of up to 16 and based on buffer max cap. [13:39 UTC] [INFO CTS-0030] Number of static layers: 0. [13:39 UTC] [INFO CTS-0020] Wire segment unit: 16800 dbu (16 um). [13:39 UTC] [INFO CTS-0204] A clustering solution was found from clustering size of 16 and max clustering diameter of 281. [13:39 UTC] [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. [13:39 UTC] [INFO CTS-0019] Total number of sinks after clustering: 82. [13:39 UTC] [INFO CTS-0024] Normalized sink region: [(29.4051, 45.7009), (82.9942, 97.5259)]. [13:39 UTC] [INFO CTS-0025] Width: 53.5892. [13:39 UTC] [INFO CTS-0026] Height: 51.8250. [13:39 UTC] Level 1 [13:39 UTC] Direction: Horizontal [13:39 UTC] Sinks per sub-region: 41 [13:39 UTC] Sub-region size: 26.7946 X 51.8250 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 14. [13:39 UTC] Level 2 [13:39 UTC] Direction: Vertical [13:39 UTC] Sinks per sub-region: 21 [13:39 UTC] Sub-region size: 26.7946 X 25.9125 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 12. [13:39 UTC] Level 3 [13:39 UTC] Direction: Horizontal [13:39 UTC] Sinks per sub-region: 11 [13:39 UTC] Sub-region size: 13.3973 X 25.9125 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 6. [13:39 UTC] [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (3350.871 um) and max number of sinks is 15. [13:39 UTC] [INFO CTS-0035] Number of sinks covered: 82. [13:39 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:39 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_jtag_tck_i. [13:39 UTC] [INFO CTS-0028] Total number of sinks: 1. [13:39 UTC] [INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 833.3 um. [13:39 UTC] [INFO CTS-0030] Number of static layers: 0. [13:39 UTC] [INFO CTS-0020] Wire segment unit: 16800 dbu (16 um). [13:39 UTC] [INFO CTS-0023] Original sink region: [(311445, 1057090), (311445, 1057090)]. [13:39 UTC] [INFO CTS-0024] Normalized sink region: [(18.5384, 62.922), (18.5384, 62.922)]. [13:39 UTC] [INFO CTS-0025] Width: 0.0000. [13:39 UTC] [INFO CTS-0026] Height: 0.0000. [13:39 UTC] Level 1 [13:39 UTC] Direction: Vertical [13:39 UTC] Sinks per sub-region: 1 [13:39 UTC] Sub-region size: 0.0000 X 0.0000 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 1. [13:39 UTC] [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (3350.871 um) and max number of sinks is 15. [13:39 UTC] [INFO CTS-0035] Number of sinks covered: 1. [13:39 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:39 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_jtag_tck_i_regs. [13:39 UTC] [INFO CTS-0028] Total number of sinks: 149. [13:39 UTC] [INFO CTS-0060] Register sinks will be clustered in groups of up to 16 and based on buffer max cap. [13:39 UTC] [INFO CTS-0030] Number of static layers: 0. [13:39 UTC] [INFO CTS-0020] Wire segment unit: 16800 dbu (16 um). [13:39 UTC] [INFO CTS-0023] Original sink region: [(410532, 972710), (595737, 1215042)]. [13:39 UTC] [INFO CTS-0024] Normalized sink region: [(24.4364, 57.8994), (35.4605, 72.3239)]. [13:39 UTC] [INFO CTS-0025] Width: 11.0241. [13:39 UTC] [INFO CTS-0026] Height: 14.4245. [13:39 UTC] Level 1 [13:39 UTC] Direction: Vertical [13:39 UTC] Sinks per sub-region: 75 [13:39 UTC] Sub-region size: 11.0241 X 7.2123 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 4. [13:39 UTC] Level 2 [13:39 UTC] Direction: Horizontal [13:39 UTC] Sinks per sub-region: 38 [13:39 UTC] Sub-region size: 5.5121 X 7.2123 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 2. [13:39 UTC] Level 3 [13:39 UTC] Direction: Vertical [13:39 UTC] Sinks per sub-region: 19 [13:39 UTC] Sub-region size: 5.5121 X 3.6061 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 2. [13:39 UTC] Level 4 [13:39 UTC] Direction: Horizontal [13:39 UTC] Sinks per sub-region: 10 [13:39 UTC] Sub-region size: 2.7560 X 3.6061 [13:39 UTC] [INFO CTS-0034] Segment length (rounded): 1. [13:39 UTC] [INFO CTS-0038] Stop criterion found. Sink region hpwl is smaller than max wirelength (3350.871 um) and max number of sinks is 15. [13:39 UTC] [INFO CTS-0035] Number of sinks covered: 149. [13:39 UTC] [INFO CTS-0018] Created 3 clock buffers. [13:39 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [13:39 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [13:39 UTC] [INFO CTS-0015] Created 3 clock nets. [13:39 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 1:2.. [13:39 UTC] [INFO CTS-0017] Max level of the clock tree: 1. [13:39 UTC] [INFO CTS-0018] Created 95 clock buffers. [13:39 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 4. [13:39 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 4. [13:39 UTC] [INFO CTS-0015] Created 95 clock nets. [13:39 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 3:1, 5:1, 7:1, 8:2, 9:3, 11:1, 12:4, 13:6, 14:7, 15:13, 16:51.. [13:39 UTC] [INFO CTS-0017] Max level of the clock tree: 3. [13:39 UTC] [INFO CTS-0018] Created 2 clock buffers. [13:39 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [13:39 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [13:39 UTC] [INFO CTS-0015] Created 2 clock nets. [13:39 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 1:1.. [13:39 UTC] [INFO CTS-0017] Max level of the clock tree: 1. [13:39 UTC] [INFO CTS-0018] Created 17 clock buffers. [13:39 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [13:39 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [13:39 UTC] [INFO CTS-0015] Created 17 clock nets. [13:39 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 6:2, 7:1, 8:5, 9:2, 10:1, 11:3, 14:1, 15:1.. [13:39 UTC] [INFO CTS-0017] Max level of the clock tree: 4. [13:39 UTC] [INFO CTS-0098] Clock net "soc_clk_i" [13:39 UTC] [INFO CTS-0099] Sinks 2 [13:39 UTC] [INFO CTS-0100] Leaf buffers 0 [13:39 UTC] [INFO CTS-0101] Average sink wire length 1529.84 um [13:39 UTC] [INFO CTS-0102] Path depth 2 - 2 [13:39 UTC] [INFO CTS-0207] Dummy loads inserted 0 [13:39 UTC] [INFO CTS-0098] Clock net "soc_clk_i_regs" [13:39 UTC] [INFO CTS-0099] Sinks 1295 [13:39 UTC] [INFO CTS-0100] Leaf buffers 82 [13:39 UTC] [INFO CTS-0101] Average sink wire length 725.78 um [13:39 UTC] [INFO CTS-0102] Path depth 3 - 4 [13:39 UTC] [INFO CTS-0207] Dummy loads inserted 73 [13:39 UTC] [INFO CTS-0124] Clock net "soc_jtag_tck_i" [13:39 UTC] [INFO CTS-0125] Sinks 1 [13:39 UTC] [INFO CTS-0098] Clock net "soc_jtag_tck_i_regs" [13:39 UTC] [INFO CTS-0099] Sinks 164 [13:39 UTC] [INFO CTS-0100] Leaf buffers 0 [13:39 UTC] [INFO CTS-0101] Average sink wire length 170.46 um [13:39 UTC] [INFO CTS-0102] Path depth 2 - 2 [13:39 UTC] [INFO CTS-0207] Dummy loads inserted 15 [13:39 UTC] [INFO CTS-0033] Balancing latency for clock clk_jtg [13:39 UTC] [INFO CTS-0036] inserted 0 delay buffers [13:39 UTC] [INFO CTS-0033] Balancing latency for clock clk_sys [13:39 UTC] [INFO CTS-0036] inserted 0 delay buffers [13:39 UTC] [INFO CTS-0500] Runtime: 17.59s [13:39 UTC] Detailed placement [13:39 UTC] [INFO DPL-0006] Core area: 1938497.70 um^2 [13:39 UTC] [INFO DPL-0007] Movable instances area: 314617.16 um^2 [13:39 UTC] [INFO DPL-0008] Fixed instances area within core: 192169.76 um^2 [13:39 UTC] [INFO DPL-0009] Utilization: 26.1% [13:39 UTC] [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [13:39 UTC] [INFO DPL-1102] Legalizing using negotiation legalizer. [13:39 UTC] [INFO DPL-1103] Negotiation base search window: +/-20 sites horizontally, +/-5 rows vertically [13:39 UTC] Automatic search window extension enabled. [13:39 UTC] Search window extendable up to the max displacement cap of +/-500 sites, +/-100 rows near walls. [13:39 UTC] [INFO DPL-1104] NegotiationLegalizer DRC penalty: 5. [13:39 UTC] [INFO DPL-0392] Negotiation cell height distribution (3 unique row-count(s)): [13:39 UTC] [INFO DPL-0393] height 1 row(s): 31729 cells [13:39 UTC] [INFO DPL-0393] height 2 row(s): 940 cells [13:39 UTC] [INFO DPL-0393] height 57 row(s): 2 cells [13:39 UTC] | Total | Illegal | Illegal [13:39 UTC] Iteration | Violations | Cells | Sites [13:39 UTC] --------------------------------------------- [13:39 UTC] 0 | 1258 | 182 | 1067 [13:39 UTC] 1 | 309 | 39 | 270 [13:39 UTC] 2 | 229 | 17 | 212 [13:39 UTC] 3 | 73 | 7 | 66 [13:39 UTC] 4 | 54 | 2 | 52 [13:39 UTC] 5 | 32 | 2 | 30 [13:39 UTC] 6 | 36 | 2 | 34 [13:39 UTC] 7 | 0 | 0 | 0 [13:39 UTC] Negotiation phase 1 converged at iteration 7. [13:39 UTC] [INFO DPL-0500] Runtime: 0.47s [13:39 UTC] Placement Analysis [13:39 UTC] --------------------------------- [13:39 UTC] total displacement 24775.0 u [13:39 UTC] average displacement 0.8 u [13:39 UTC] max displacement 22.3 u [13:39 UTC] original HPWL 1068749.1 u [13:39 UTC] legalized HPWL 1082423.7 u [13:39 UTC] delta HPWL 1 % [13:39 UTC] [13:39 UTC] Estimate parasitics [13:39 UTC] Warning: There are 56 unconstrained endpoints. [13:39 UTC] Repair setup [13:39 UTC] [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [13:39 UTC] [INFO RSZ-0094] Found 196 endpoints with setup violations. [13:39 UTC] [INFO RSZ-0099] Repairing 196 out of 196 (100.00%) violating endpoints... [13:39 UTC] Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | StTNS | EnTNS | Viol | Worst [13:39 UTC] | Buffers | Gates | Buffers | Gates | Swaps | | | | | Endpts | St/EnPt [13:39 UTC] ------------------------------------------------------------------------------------------------------------------------------ [13:39 UTC] 0* | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.282 | -5.8 | -22.4 | 196 | _tray_size4_8464/D2 [13:39 UTC] 4* | 0 | 3 | 0 | 0 | 0 | +0.0% | -0.020 | -0.0 | -0.1 | 196 | _tray_size4_8464/D2 [13:39 UTC] 9* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 10* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 10* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 11* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 12* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 13* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 14* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 15* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 16* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 17* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 18* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 19* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 20* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 20* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 21* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 22* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 23* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 24* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 25* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 26* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 27* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 28* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 29* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 30* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 30* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 31* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 32* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 33* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 34* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 35* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 36* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 37* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 38* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 39* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 40* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 40* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 41* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 42* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 43* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 44* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 45* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 46* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 47* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 48* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 49* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 50* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 50* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 51* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 52* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 53* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 54* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 55* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 56* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 57* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 58* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 59* | 0 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| 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 104* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 105* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 106* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 107* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 108* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 109* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 110* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 110* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 111* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 112* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 113* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 114* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 115* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 116* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 117* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 118* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 119* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 120* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 120* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 121* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 122* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 123* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 124* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 125* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 126* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 127* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 128* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 129* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 130* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 130* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 131* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 132* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 133* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 134* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 135* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 136* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 137* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 138* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 139* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 140* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 140* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 141* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 142* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 143* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 144* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 145* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 146* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 147* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 148* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 149* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 150* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 150* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 151* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 152* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 153* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 154* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 155* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 156* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 157* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 158* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 159* | 0 | 4 | 5 | 0 | 1 | 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0.0 | 0.0 | 196 | status_o [13:39 UTC] 170* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 171* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 172* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 173* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 174* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 175* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 176* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 177* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 178* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 179* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 180* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 180* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 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[13:39 UTC] 192* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 193* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 194* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 195* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 196* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 197* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 198* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 199* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 200* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 200* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 201* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 202* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 203* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] 203* | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 196 | status_o [13:39 UTC] final | 0 | 4 | 5 | 0 | 1 | +0.0% | 0.013 | 0.0 | 0.0 | 0 | status_o [13:39 UTC] ------------------------------------------------------------------------------------------------------------------------------ [13:39 UTC] [INFO RSZ-0040] Inserted 5 buffers. [13:39 UTC] [INFO RSZ-0051] Resized 4 instances: 4 up, 0 up match, 0 down, 0 VT [13:39 UTC] [INFO RSZ-0043] Swapped pins on 1 instances. [13:39 UTC] [INFO RSZ-0505] Runtime: 5.68s [13:39 UTC] Detailed placement [13:39 UTC] [INFO DPL-0006] Core area: 1938497.70 um^2 [13:39 UTC] [INFO DPL-0007] Movable instances area: 314659.50 um^2 [13:39 UTC] [INFO DPL-0008] Fixed instances area within core: 192169.76 um^2 [13:39 UTC] [INFO DPL-0009] Utilization: 26.1% [13:39 UTC] [INFO DPL-0005] Diamond search max displacement: +/- 500 sites horizontally, +/- 100 rows vertically. [13:39 UTC] [INFO DPL-1102] Legalizing using negotiation legalizer. [13:39 UTC] [INFO DPL-1103] Negotiation base search window: +/-20 sites horizontally, +/-5 rows vertically [13:39 UTC] Automatic search window extension enabled. [13:39 UTC] Search window extendable up to the max displacement cap of +/-500 sites, +/-100 rows near walls. [13:39 UTC] [INFO DPL-1104] NegotiationLegalizer DRC penalty: 5. [13:39 UTC] [INFO DPL-0392] Negotiation cell height distribution (3 unique row-count(s)): [13:39 UTC] [INFO DPL-0393] height 1 row(s): 31734 cells [13:39 UTC] [INFO DPL-0393] height 2 row(s): 940 cells [13:39 UTC] [INFO DPL-0393] height 57 row(s): 2 cells [13:39 UTC] | Total | Illegal | Illegal [13:39 UTC] Iteration | Violations | Cells | Sites [13:39 UTC] --------------------------------------------- [13:39 UTC] 0 | 24 | 6 | 18 [13:39 UTC] 1 | 0 | 0 | 0 [13:39 UTC] Negotiation phase 1 converged at iteration 1. [13:39 UTC] [INFO DPL-0500] Runtime: 0.25s [13:39 UTC] Placement Analysis [13:39 UTC] --------------------------------- [13:39 UTC] total displacement 22.1 u [13:39 UTC] average displacement 0.0 u [13:39 UTC] max displacement 8.8 u [13:39 UTC] original HPWL 1082665.3 u [13:39 UTC] legalized HPWL 1082675.1 u [13:39 UTC] delta HPWL 0 % [13:39 UTC] [13:39 UTC] Check placement [13:39 UTC] Estimate parasitics [13:39 UTC] Warning: There are 56 unconstrained endpoints. [13:39 UTC] Saving checkpoint 03_croc.cts [13:39 UTC] Time: 57.444379 sec deltaT: 57.375557 [13:39 UTC] saving image to reports/03_croc.cts.png [13:39 UTC] [INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode [13:39 UTC] [INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode [13:39 UTC] [INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode [13:39 UTC] ############################################################################### [13:39 UTC] # Stage 03 complete: Checkpoint saved to save/03_croc.cts.zip [13:39 UTC] ###############################################################################