[INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][OpenROAD] Running scripts/03_cts.tcl [13:27 UTC] OpenROAD v2.0-27244-gfecb04286 [13:27 UTC] Features included (+) or not (-): +GPU +GUI +Python [13:27 UTC] This program is licensed under the BSD-3 license. See the LICENSE file for details. [13:27 UTC] Components of this program may be licensed under more restrictive licenses which must be honored. [13:27 UTC] Setting up project croc [13:27 UTC] - Netlist: ../yosys/out/croc_yosys.v [13:27 UTC] - Project: croc [13:27 UTC] - Top design: croc_chip [13:27 UTC] - Report directory: reports [13:27 UTC] - Save directory: save [13:27 UTC] - Output directory: out [13:27 UTC] Init standard cells [13:27 UTC] Init IO cells [13:27 UTC] Init SRAM macros [13:27 UTC] Init tech-lef [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13cmos5l_tech.lef, created 15 layers, 52 vias [13:27 UTC] Init cell-lef [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13g2_stdcell.lef, created 84 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13cmos5l_io.lef, created 22 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/bondpad5l_70x70.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_64x64_c2_bm_bist.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_2048x64_c2_bm_bist.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_1024x64_c2_bm_bist.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_512x64_c2_bm_bist.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_256x64_c2_bm_bist.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef, created 1 library cells [13:27 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_256x48_c2_bm_bist.lef, created 1 library cells [13:27 UTC] Loading checkpoint 02_croc.placed [13:27 UTC] Loading from ZIP file: save/02_croc.placed.zip [13:27 UTC] ############################################################################### [13:27 UTC] # Stage 03: CLOCK TREE SYNTHESIS [13:27 UTC] ############################################################################### [13:27 UTC] Repair clock inverters [13:27 UTC] Clock Tree Synthesis [13:27 UTC] [INFO CTS-0050] Root buffer is sg13g2_buf_8. [13:27 UTC] [INFO CTS-0051] Sink buffer is sg13g2_buf_16. [13:27 UTC] [INFO CTS-0052] The following clock buffers will be used for CTS: [13:27 UTC] sg13g2_buf_2 [13:27 UTC] sg13g2_buf_4 [13:27 UTC] sg13g2_buf_8 [13:27 UTC] sg13g2_buf_16 [13:27 UTC] [INFO CTS-0049] Characterization buffer is sg13g2_buf_16. [13:27 UTC] [INFO CTS-0007] Net "clk_i" found for clock "clk_sys". [13:27 UTC] [INFO CTS-0116] Special net "clk_i" skipped. [13:27 UTC] [INFO CTS-0011] Clock net "soc_clk_i" for macros has 2 sinks. [13:27 UTC] [INFO CTS-0011] Clock net "soc_clk_i_regs" for registers has 3985 sinks. [13:27 UTC] [INFO CTS-0007] Net "jtag_tck_i" found for clock "clk_jtg". [13:27 UTC] [INFO CTS-0116] Special net "jtag_tck_i" skipped. [13:27 UTC] [INFO CTS-0011] Clock net "soc_jtag_tck_i" for macros has 1 sinks. [13:27 UTC] [INFO CTS-0011] Clock net "soc_jtag_tck_i_regs" for registers has 289 sinks. [13:27 UTC] [INFO CTS-0010] Clock net "i_croc_soc/i_croc/i_dmi_jtag/i_dmi_jtag_tap.tck_n" has 2 sinks. [13:27 UTC] [INFO CTS-0007] Net "ref_clk_i" found for clock "clk_rtc". [13:27 UTC] [INFO CTS-0116] Special net "ref_clk_i" skipped. [13:27 UTC] [WARNING CTS-0041] Net "soc_ref_clk_i" has 1 sinks. Skipping... [13:27 UTC] [INFO CTS-0008] TritonCTS found 5 clock nets. [13:27 UTC] [INFO CTS-0097] Characterization used 4 buffer(s) types. [13:27 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:27 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_clk_i. [13:27 UTC] [INFO CTS-0028] Total number of sinks: 2. [13:27 UTC] [INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 833.3 um. [13:27 UTC] [INFO CTS-0030] Number of static layers: 0. [13:27 UTC] [INFO CTS-0020] Wire segment unit: 18900 dbu (18 um). [13:27 UTC] [INFO CTS-0023] Original sink region: [(552850, 1372610), (1351890, 1372610)]. [13:27 UTC] [INFO CTS-0024] Normalized sink region: [(29.2513, 72.6249), (71.5286, 72.6249)]. [13:27 UTC] [INFO CTS-0025] Width: 42.2772. [13:27 UTC] [INFO CTS-0026] Height: 0.0000. [13:27 UTC] Level 1 [13:27 UTC] Direction: Horizontal [13:27 UTC] Sinks per sub-region: 1 [13:27 UTC] Sub-region size: 21.1386 X 0.0000 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 10. [13:27 UTC] [INFO CTS-0032] Stop criterion found. Max number of sinks is 8. [13:27 UTC] [INFO CTS-0035] Number of sinks covered: 2. [13:27 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:27 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_clk_i_regs. [13:27 UTC] [INFO CTS-0028] Total number of sinks: 3985. [13:27 UTC] [INFO CTS-0090] Sinks will be clustered based on buffer max cap. [13:27 UTC] [INFO CTS-0030] Number of static layers: 0. [13:27 UTC] [INFO CTS-0020] Wire segment unit: 18900 dbu (18 um). [13:27 UTC] [INFO CTS-0206] Best clustering solution was found from clustering size of 8 and clustering diameter of 50. [13:27 UTC] [INFO CTS-0019] Total number of sinks after clustering: 192. [13:27 UTC] [INFO CTS-0024] Normalized sink region: [(19.6074, 24.1082), (82.3162, 82.7241)]. [13:27 UTC] [INFO CTS-0025] Width: 62.7088. [13:27 UTC] [INFO CTS-0026] Height: 58.6159. [13:27 UTC] Level 1 [13:27 UTC] Direction: Horizontal [13:27 UTC] Sinks per sub-region: 96 [13:27 UTC] Sub-region size: 31.3544 X 58.6159 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 16. [13:27 UTC] Level 2 [13:27 UTC] Direction: Vertical [13:27 UTC] Sinks per sub-region: 48 [13:27 UTC] Sub-region size: 31.3544 X 29.3079 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 14. [13:27 UTC] Level 3 [13:27 UTC] Direction: Horizontal [13:27 UTC] Sinks per sub-region: 24 [13:27 UTC] Sub-region size: 15.6772 X 29.3079 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 8. [13:27 UTC] Level 4 [13:27 UTC] Direction: Vertical [13:27 UTC] Sinks per sub-region: 12 [13:27 UTC] Sub-region size: 15.6772 X 14.6540 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 8. [13:27 UTC] Level 5 [13:27 UTC] Direction: Horizontal [13:27 UTC] Sinks per sub-region: 6 [13:27 UTC] Sub-region size: 7.8386 X 14.6540 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 4. [13:27 UTC] [INFO CTS-0032] Stop criterion found. Max number of sinks is 8. [13:27 UTC] [INFO CTS-0035] Number of sinks covered: 192. [13:27 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:27 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_jtag_tck_i. [13:27 UTC] [INFO CTS-0028] Total number of sinks: 1. [13:27 UTC] [INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 833.3 um. [13:27 UTC] [INFO CTS-0030] Number of static layers: 0. [13:27 UTC] [INFO CTS-0020] Wire segment unit: 18900 dbu (18 um). [13:27 UTC] [INFO CTS-0023] Original sink region: [(347796, 568392), (347796, 568392)]. [13:27 UTC] [INFO CTS-0024] Normalized sink region: [(18.4019, 30.0737), (18.4019, 30.0737)]. [13:27 UTC] [INFO CTS-0025] Width: 0.0000. [13:27 UTC] [INFO CTS-0026] Height: 0.0000. [13:27 UTC] Level 1 [13:27 UTC] Direction: Vertical [13:27 UTC] Sinks per sub-region: 1 [13:27 UTC] Sub-region size: 0.0000 X 0.0000 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 1. [13:27 UTC] [INFO CTS-0032] Stop criterion found. Max number of sinks is 8. [13:27 UTC] [INFO CTS-0035] Number of sinks covered: 1. [13:27 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:27 UTC] [INFO CTS-0027] Generating H-Tree topology for net soc_jtag_tck_i_regs. [13:27 UTC] [INFO CTS-0028] Total number of sinks: 289. [13:27 UTC] [INFO CTS-0090] Sinks will be clustered based on buffer max cap. [13:27 UTC] [INFO CTS-0030] Number of static layers: 0. [13:27 UTC] [INFO CTS-0020] Wire segment unit: 18900 dbu (18 um). [13:27 UTC] [INFO CTS-0206] Best clustering solution was found from clustering size of 8 and clustering diameter of 50. [13:27 UTC] [INFO CTS-0019] Total number of sinks after clustering: 11. [13:27 UTC] [INFO CTS-0024] Normalized sink region: [(18.1968, 23.6944), (23.7499, 45.2411)]. [13:27 UTC] [INFO CTS-0025] Width: 5.5531. [13:27 UTC] [INFO CTS-0026] Height: 21.5467. [13:27 UTC] Level 1 [13:27 UTC] Direction: Vertical [13:27 UTC] Sinks per sub-region: 6 [13:27 UTC] Sub-region size: 5.5531 X 10.7734 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 6. [13:27 UTC] [INFO CTS-0032] Stop criterion found. Max number of sinks is 8. [13:27 UTC] [INFO CTS-0035] Number of sinks covered: 11. [13:27 UTC] [INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used. [13:27 UTC] [INFO CTS-0027] Generating H-Tree topology for net i_croc_soc\/i_croc\/i_dmi_jtag\/i_dmi_jtag_tap.tck_n. [13:27 UTC] [INFO CTS-0028] Total number of sinks: 2. [13:27 UTC] [INFO CTS-0090] Sinks will be clustered based on buffer max cap. [13:27 UTC] [INFO CTS-0030] Number of static layers: 0. [13:27 UTC] [INFO CTS-0020] Wire segment unit: 18900 dbu (18 um). [13:27 UTC] [INFO CTS-0023] Original sink region: [(344160, 565320), (347040, 568680)]. [13:27 UTC] [INFO CTS-0024] Normalized sink region: [(18.2095, 29.9111), (18.3619, 30.0889)]. [13:27 UTC] [INFO CTS-0025] Width: 0.1524. [13:27 UTC] [INFO CTS-0026] Height: 0.1778. [13:27 UTC] Level 1 [13:27 UTC] Direction: Vertical [13:27 UTC] Sinks per sub-region: 1 [13:27 UTC] Sub-region size: 0.1524 X 0.0889 [13:27 UTC] [INFO CTS-0034] Segment length (rounded): 1. [13:27 UTC] [INFO CTS-0032] Stop criterion found. Max number of sinks is 8. [13:27 UTC] [INFO CTS-0035] Number of sinks covered: 2. [13:27 UTC] [INFO CTS-0018] Created 3 clock buffers. [13:27 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [13:27 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [13:27 UTC] [INFO CTS-0015] Created 3 clock nets. [13:27 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 1:2.. [13:27 UTC] [INFO CTS-0017] Max level of the clock tree: 1. [13:27 UTC] [INFO CTS-0018] Created 228 clock buffers. [13:27 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 3. [13:27 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 4. [13:27 UTC] [INFO CTS-0015] Created 228 clock nets. [13:27 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 5:1, 6:32, 14:3, 15:1, 16:7, 17:7, 18:15, 19:17, 20:27, 21:29, 22:29, 23:25, 24:19, 25:7, 26:3, 27:1.. [13:27 UTC] [INFO CTS-0017] Max level of the clock tree: 5. [13:27 UTC] [INFO CTS-0018] Created 2 clock buffers. [13:27 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [13:27 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [13:27 UTC] [INFO CTS-0015] Created 2 clock nets. [13:27 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 1:1.. [13:27 UTC] [INFO CTS-0017] Max level of the clock tree: 1. [13:27 UTC] [INFO CTS-0018] Created 14 clock buffers. [13:27 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 3. [13:27 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 3. [13:27 UTC] [INFO CTS-0015] Created 14 clock nets. [13:27 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 5:1, 6:1, 8:1, 24:1, 25:1, 26:1, 27:2, 30:4, 32:1.. [13:27 UTC] [INFO CTS-0017] Max level of the clock tree: 1. [13:27 UTC] [INFO CTS-0018] Created 3 clock buffers. [13:27 UTC] [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [13:27 UTC] [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [13:27 UTC] [INFO CTS-0015] Created 3 clock nets. [13:27 UTC] [INFO CTS-0016] Fanout distribution for the current clock = 1:2.. [13:27 UTC] [INFO CTS-0017] Max level of the clock tree: 1. [13:27 UTC] [INFO CTS-0098] Clock net "soc_clk_i" [13:27 UTC] [INFO CTS-0099] Sinks 2 [13:27 UTC] [INFO CTS-0100] Leaf buffers 0 [13:27 UTC] [INFO CTS-0101] Average sink wire length 1396.15 um [13:27 UTC] [INFO CTS-0102] Path depth 2 - 2 [13:27 UTC] [INFO CTS-0207] Dummy loads inserted 0 [13:27 UTC] [INFO CTS-0098] Clock net "soc_clk_i_regs" [13:27 UTC] [INFO CTS-0099] Sinks 4135 [13:27 UTC] [INFO CTS-0100] Leaf buffers 191 [13:27 UTC] [INFO CTS-0101] Average sink wire length 797.51 um [13:27 UTC] [INFO CTS-0102] Path depth 3 - 4 [13:27 UTC] [INFO CTS-0207] Dummy loads inserted 150 [13:27 UTC] [INFO CTS-0124] Clock net "soc_jtag_tck_i" [13:27 UTC] [INFO CTS-0125] Sinks 1 [13:27 UTC] [INFO CTS-0098] Clock net "soc_jtag_tck_i_regs" [13:27 UTC] [INFO CTS-0099] Sinks 298 [13:27 UTC] [INFO CTS-0100] Leaf buffers 11 [13:27 UTC] [INFO CTS-0101] Average sink wire length 284.35 um [13:27 UTC] [INFO CTS-0102] Path depth 2 - 3 [13:27 UTC] [INFO CTS-0207] Dummy loads inserted 9 [13:27 UTC] [INFO CTS-0098] Clock net "i_croc_soc\/i_croc\/i_dmi_jtag\/i_dmi_jtag_tap.tck_n" [13:27 UTC] [INFO CTS-0099] Sinks 2 [13:27 UTC] [INFO CTS-0100] Leaf buffers 0 [13:27 UTC] [INFO CTS-0101] Average sink wire length 38.19 um [13:27 UTC] [INFO CTS-0102] Path depth 2 - 2 [13:27 UTC] [INFO CTS-0207] Dummy loads inserted 0 [13:27 UTC] [INFO CTS-0033] Balancing latency for clock clk_jtg [13:27 UTC] [INFO CTS-0036] inserted 0 delay buffers [13:27 UTC] [INFO CTS-0033] Balancing latency for clock clk_sys [13:27 UTC] [INFO CTS-0036] inserted 0 delay buffers [13:27 UTC] Detailed placement [13:27 UTC] Placement Analysis [13:27 UTC] --------------------------------- [13:27 UTC] total displacement 4103.4 u [13:27 UTC] average displacement 0.1 u [13:27 UTC] max displacement 15.5 u [13:27 UTC] original HPWL 1493838.2 u [13:27 UTC] legalized HPWL 1515780.0 u [13:27 UTC] delta HPWL 1 % [13:27 UTC] [13:27 UTC] Estimate parasitics [13:27 UTC] Repair setup [13:27 UTC] [INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove [13:27 UTC] [INFO RSZ-0098] No setup violations found [13:27 UTC] Detailed placement [13:27 UTC] Placement Analysis [13:27 UTC] --------------------------------- [13:27 UTC] total displacement 0.0 u [13:27 UTC] average displacement 0.0 u [13:27 UTC] max displacement 0.0 u [13:27 UTC] original HPWL 1515780.0 u [13:27 UTC] legalized HPWL 1515780.0 u [13:27 UTC] delta HPWL 0 % [13:27 UTC] [13:27 UTC] Check placement [13:27 UTC] Estimate parasitics [13:27 UTC] Saving checkpoint 03_croc.cts [13:28 UTC] Time: 39.804636 sec deltaT: 39.752345 [13:28 UTC] saving image to reports/03_croc.cts.png [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [13:28 UTC] [INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode [13:28 UTC] [INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode [13:28 UTC] [INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode [13:28 UTC] ############################################################################### [13:28 UTC] # Stage 03 complete: Checkpoint saved to save/03_croc.cts.zip [13:28 UTC] ###############################################################################