Croc SoC Flow Report

29b2e74sg13cmos5l

GitHub

Chip

Croc chip layout with module outlines. Open full-size modules PNG Rendered layout of the Croc chip die from the Full Flow GDS, showing the pad ring, macros and standard-cell core. Open full-size render PNG
Open map
Sealed 2000 µmSealed 2000 µmCore 1255.68 µmCore 1251.18 µm
Chip view

Modules PNG SVG PDF Render PNG PDF Open map

Area

CellsCountArea (µm²)Area (GE)
Logic cells34,176536,60773,937
Macros2159,44021,969
Signal + power pads64921,600126,984
Total34,2421,617,647222,890

1 GE = 7.2576 µm² (NAND2). Excludes fillers, antenna cells, corners and bondpads.

Module logic area
ModuleCellsArea (µm²)Area (GE)
Core11,790214,65129,576
Other logic11,091124,31517,129
Debug4,76872,92110,048
UART2,06243,7806,032
JTAG2,04238,0085,237
GPIO1,37726,9083,707
Timer58210,3291,423
ROM3714,169574
User931,526210

Logic cell footprints. Macros excluded.

Design

MetricValue
Clock target100 MHz
Worst setup slack+1.12 ns
Setup / hold violations0 / 0
SRAM4 KiB
Core area1,571,082 µm²
Core utilization44.31%

Verification

Verilator · RTL and post-Yosys netlist · JTAG boot/result handshake
TestExercisesRTLNetlist
Default configuration
helloworldBoot, SRAM load and UART transmitPassPass
print_configConfiguration register readbackPassPass
iDMA configuration
test_clintTime counter, compare and software-interrupt registersPassPass
test_computeInteger arithmetic, shifts and logicPassPass
test_gpioOutput, pin loopback and togglePassPass
test_idmaSRAM copy and 2D transferPassPass
test_interruptsTrap vector and handler dispatchPassPass
test_obi_timerCount, compare and auto-resetPassPass
test_soc_ctrlBoot address and targetPassPass
test_uartTransmit and internal loopback; not external RXPassPass
DRC

Pass0 violations

Minimal metal, pin, angle and forbidden-geometry checks. Off-grid and recommended checks excluded.

Runtime

Full Flow

Design flow; backend wall time. Simulation branches are not in the total.

  1. RTLSource
    RTL simulation1m9sPass
    FPGA (Genesys2)18m41sPass
  2. Synthesis3m37s2.6%
    Netlist simulation10m15sPass
  3. Floorplan6s0.1%
  4. Placement4m57s3.6%
  5. CTS40s0.5%
  6. Routing1h55m16s82.7%
  7. Finishing18s0.2%
  8. GDS + seal17s0.2%
  9. Minimal DRC14m10s10.2%
  1. Synthesis, 2.6%
  2. Floorplan, 0.1%
  3. Placement, 3.6%
  4. CTS, 0.5%
  5. Routing, 82.7%
  6. Finishing, 0.2%
  7. GDS + seal, 0.2%
  8. Minimal DRC, 10.2%

Backend stage wall time2h19m21s

CI reports: Full Flow · Simulation · FPGA

Durations
StageSecondsShare
Synthesis217.2002.6%
Floorplan6.4300.1%
Placement297.4583.6%
CTS40.4760.5%
Routing6915.83982.7%
Finishing17.5290.2%
GDS + seal16.6380.2%
Minimal DRC849.55510.2%
Backend stages8361.125100%

Measured stage wall time. Setup and PDK downloads excluded.