Croc SoC Flow Report

Chip

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Chip view Modules Render Map

Dimensions

Cells	Count	Area (µm²)	Area (GE)
Logic cells	25,184	316,141	56,006
Macros	2	159,440	28,245
Signal + power pads	64	921,600	163,265
Total	25,250	1,397,181	247,516

1 GE = 5.6448 µm² (NAND2). Excludes fillers, antenna cells, corners and bondpads.

Module logic area

Module	Cells	Area (µm²)	Area (GE)
Other logic	6,505	140,191	24,836
Core	10,047	95,490	16,917
Debug	3,421	30,094	5,331
JTAG	2,020	19,411	3,439
UART	1,362	14,499	2,569
GPIO	974	9,039	1,601
Timer	463	4,225	749
ROM	323	2,554	453
User	69	638	113

Logic cell footprints. Macros excluded.

Verilator · RTL and post-Yosys netlist · JTAG boot/result handshake
Test	Exercises	RTL	Netlist
Default configuration
helloworld	Boot, SRAM load and UART transmit	Pass	Pass
print_config	Configuration register readback	Pass	Pass
iDMA configuration
test_clint	Time counter, compare and software-interrupt registers	Pass	Pass
test_compute	Integer arithmetic, shifts and logic	Pass	Pass
test_gpio	Output, pin loopback and toggle	Pass	Pass
test_idma	SRAM copy and 2D transfer	Pass	Pass
test_interrupts	Trap vector and handler dispatch	Pass	Pass
test_obi_timer	Count, compare and auto-reset	Pass	Pass
test_soc_ctrl	Boot address and target	Pass	Pass
test_uart	Transmit and internal loopback; not external RX	Pass	Pass

DRC

Pass0 violations

Minimal metal, pin, angle and forbidden-geometry checks. Off-grid and recommended checks excluded.

Design flow; backend wall time. Simulation branches are not in the total.

Backend stage wall time2h16m25s

Durations

Measured stage wall time. Setup and PDK downloads excluded.