[INFO][ENV] Croc root: /fosic/designs/croc [INFO][ENV] PDK root: /fosic/designs/croc/technology [INFO][ENV] Croc PDK: sg13cmos5l [INFO][ENV] Active technology view: public mirror [INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout [INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1 [INFO][ENV] Tech LEF: sg13cmos5l_tech.lef [INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds [INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib [INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds [INFO][OpenROAD] Running scripts/05_finishing.tcl [15:23 UTC] OpenROAD v2.0-27244-gfecb04286 [15:23 UTC] Features included (+) or not (-): +GPU +GUI +Python [15:23 UTC] This program is licensed under the BSD-3 license. See the LICENSE file for details. [15:23 UTC] Components of this program may be licensed under more restrictive licenses which must be honored. [15:23 UTC] Setting up project croc [15:23 UTC] - Netlist: ../yosys/out/croc_yosys.v [15:23 UTC] - Project: croc [15:23 UTC] - Top design: croc_chip [15:23 UTC] - Report directory: reports [15:23 UTC] - Save directory: save [15:23 UTC] - Output directory: out [15:23 UTC] Init standard cells [15:23 UTC] Init IO cells [15:23 UTC] Init SRAM macros [15:23 UTC] Init tech-lef [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13cmos5l_tech.lef, created 15 layers, 52 vias [15:23 UTC] Init cell-lef [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13g2_stdcell.lef, created 84 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/sg13cmos5l_io.lef, created 22 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/bondpad5l_70x70.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_64x64_c2_bm_bist.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_2048x64_c2_bm_bist.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_1024x64_c2_bm_bist.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_512x64_c2_bm_bist.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_256x64_c2_bm_bist.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef, created 1 library cells [15:23 UTC] [INFO ODB-0227] LEF file: /fosic/designs/croc/technology/lef/RM_IHPSG13_1P_256x48_c2_bm_bist.lef, created 1 library cells [15:23 UTC] Loading checkpoint 04_croc.routed [15:23 UTC] Loading from ZIP file: save/04_croc.routed.zip [15:23 UTC] ############################################################################### [15:23 UTC] # Stage 05: FINISHING [15:23 UTC] ############################################################################### [15:23 UTC] Filler placement [15:23 UTC] [INFO DPL-0001] Placed 78151 filler instances. [15:23 UTC] Global connect [15:23 UTC] Saving checkpoint 05_croc.final [15:23 UTC] Time: 5.79916 sec deltaT: 5.746885000000001 [15:23 UTC] saving image to reports/05_croc.final.png [15:23 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [15:23 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [15:23 UTC] [WARNING GUI-0076] QStandardPaths: runtime directory '/tmp/runtime-default' is not owned by UID 1001, but a directory permissions 0777 owned by UID 0 GID 0 [15:23 UTC] Write output files [15:23 UTC] ############################################################################### [15:23 UTC] # Stage 05 complete: Final outputs written to out/ [15:23 UTC] # - DEF: out/croc.def [15:23 UTC] # - ODB: out/croc.odb [15:23 UTC] # - SDC: out/croc.sdc [15:23 UTC] # - Verilog: out/croc.v [15:23 UTC] # - LVS netlist: out/croc_lvs.v [15:23 UTC] # Checkpoint saved to save/05_croc.final.zip [15:23 UTC] ###############################################################################