ssr.h File Reference

This file contains functions to conveniently program Snitch's SSRs. More...

Go to the source code of this file.

Enumerations
enum	snrt_ssr_dm_t { SNRT_SSR_DM0 = 0 , SNRT_SSR_DM1 = 1 , SNRT_SSR_DM2 = 2 , SNRT_SSR_DM_ALL = 31 }
	The different SSRs. More...
enum	snrt_ssr_dim_t { SNRT_SSR_1D = 0 , SNRT_SSR_2D = 1 , SNRT_SSR_3D = 2 , SNRT_SSR_4D = 3 }
	The different dimensions. More...
enum	snrt_ssr_reg_t {   SNRT_SSR_REG_STATUS = 0 , SNRT_SSR_REG_REPEAT = 1 , SNRT_SSR_REG_BOUNDS = 2 , SNRT_SSR_REG_STRIDES = 6 ,   SNRT_SSR_REG_IDX_CFG = 10 , SNRT_SSR_REG_IDX_BASE = 11 , SNRT_SSR_REG_RPTR_INDIR = 16 , SNRT_SSR_REG_RPTR = 24 ,   SNRT_SSR_REG_WPTR = 28 }
	The SSR configuration registers. More...
enum	snrt_ssr_idxsize_t { SNRT_SSR_IDXSIZE_U8 = 0 , SNRT_SSR_IDXSIZE_U16 = 1 , SNRT_SSR_IDXSIZE_U32 = 2 , SNRT_SSR_IDXSIZE_U64 = 3 }
	The size of the SSSR indirection indices. More...

Functions
void	snrt_fpu_fence ()
	Synchronize the integer and float pipelines.
void	snrt_ssr_enable ()
	Enable all SSRs.
void	snrt_ssr_disable ()
	Disable all SSRs.
void	snrt_sc_enable (uint32_t mask)
	Enable scalar chaining.
void	snrt_sc_disable (uint32_t mask)
	Disable scalar chaining.
static uint32_t	read_ssr_cfg (const snrt_ssr_reg_t reg, const snrt_ssr_dm_t dm)
	Read the value of an SSR configuration register.
static void	write_ssr_cfg (const snrt_ssr_reg_t reg, const snrt_ssr_dm_t dm, uint32_t value)
	Write a value to an SSR configuration register.
static void	snrt_ssr_loop_1d (const snrt_ssr_dm_t dm, size_t b0, size_t s0)
	Configure an SSR data mover for a 1D loop nest.
static void	snrt_ssr_loop_2d (const snrt_ssr_dm_t dm, size_t b0, size_t b1, size_t s0, size_t s1)
	Configure an SSR data mover for a 2D loop nest.
static void	snrt_ssr_loop_3d (const snrt_ssr_dm_t dm, size_t b0, size_t b1, size_t b2, size_t s0, size_t s1, size_t s2)
	Configure an SSR data mover for a 3D loop nest.
static void	snrt_ssr_loop_4d (const snrt_ssr_dm_t dm, size_t b0, size_t b1, size_t b2, size_t b3, size_t s0, size_t s1, size_t s2, size_t s3)
	Configure an SSR data mover for a 4D loop nest.
static void	snrt_ssr_repeat (const snrt_ssr_dm_t dm, size_t count)
	Configure the repetition count for a stream.
static void	snrt_ssr_read (const snrt_ssr_dm_t dm, const snrt_ssr_dim_t dim, volatile void *ptr)
	Start a streaming read.
static void	snrt_ssr_write (const snrt_ssr_dm_t dm, const snrt_ssr_dim_t dim, volatile void *ptr)
	Start a streaming write.
static void	snrt_issr_set_idx_cfg (const snrt_ssr_dm_t dm, snrt_ssr_idxsize_t idxsize)
	Start a streaming indirect read.
static void	snrt_issr_set_bound (const snrt_ssr_dm_t dm, size_t bound)
static void	snrt_issr_set_ptrs (const snrt_ssr_dm_t dm, volatile void *base, volatile void *idcs)
static void	snrt_issr_read (const snrt_ssr_dm_t dm, volatile void *base, volatile void *idcs, size_t bound, snrt_ssr_idxsize_t idxsize)

Detailed Description

This file contains functions to conveniently program Snitch's SSRs.

An SSR stream can be configured to replace a store (or load) sequence as could be generated by an N-dimensional affine loop nest, e.g. the following store sequence can be mapped to a 2D write SSR:

for (int i = 0; i < b1; i++)
    for (int j = 0; j < b0; j++)
        ptr[i * s1 + j * s0] = 0;

An ISSR (Indirect SSR) stream can be configured to replace a store (or load) sequence as could be generated by:

for (int i = 0; i < bound; i++)
    base[idcs[i]] = 0;

The convenience functions provided in this file can be used to set up such access patterns. The function argument names reflect the variable names presented in these sample code snippets.

Note: The exact number of elements configured in an (I)SSR stream must be consumed. Failure to comply with this requirement will result in undefined behaviour.

Enumeration Type Documentation

snrt_ssr_dim_t

enum snrt_ssr_dim_t

The different dimensions.

Enumerator
SNRT_SSR_1D	1D stream
SNRT_SSR_2D	2D stream
SNRT_SSR_3D	3D stream
SNRT_SSR_4D	4D stream

             {
    SNRT_SSR_1D = 0, 
    SNRT_SSR_2D = 1, 
    SNRT_SSR_3D = 2, 
    SNRT_SSR_4D = 3  
} snrt_ssr_dim_t;

snrt_ssr_dm_t

enum snrt_ssr_dm_t

The different SSRs.

Enumerator
SNRT_SSR_DM0	SSR data mover 0
SNRT_SSR_DM1	SSR data mover 1
SNRT_SSR_DM2	SSR data mover 2
SNRT_SSR_DM_ALL	Write to all SSRs

             {
    SNRT_SSR_DM0 = 0,    
    SNRT_SSR_DM1 = 1,    
    SNRT_SSR_DM2 = 2,    
    SNRT_SSR_DM_ALL = 31 
} snrt_ssr_dm_t;

snrt_ssr_idxsize_t

enum snrt_ssr_idxsize_t

The size of the SSSR indirection indices.

Enumerator
SNRT_SSR_IDXSIZE_U8	Unsigned 8-bit integer
SNRT_SSR_IDXSIZE_U16	Unsigned 16-bit integer
SNRT_SSR_IDXSIZE_U32	Unsigned 32-bit integer
SNRT_SSR_IDXSIZE_U64	Unsigned 64-bit integer

             {
    SNRT_SSR_IDXSIZE_U8 = 0,  
    SNRT_SSR_IDXSIZE_U16 = 1, 
    SNRT_SSR_IDXSIZE_U32 = 2, 
    SNRT_SSR_IDXSIZE_U64 = 3, 
} snrt_ssr_idxsize_t;

snrt_ssr_reg_t

enum snrt_ssr_reg_t

The SSR configuration registers.

Enumerator
SNRT_SSR_REG_STATUS	SSR status register
SNRT_SSR_REG_REPEAT	SSR repeat register
SNRT_SSR_REG_BOUNDS	SSR bounds register
SNRT_SSR_REG_STRIDES	SSR strides register
SNRT_SSR_REG_IDX_CFG	SSSR index configuration register
SNRT_SSR_REG_IDX_BASE	SSSR base address register
SNRT_SSR_REG_RPTR_INDIR	SSSR indir. indices read ptr register
SNRT_SSR_REG_RPTR	SSR read pointer register
SNRT_SSR_REG_WPTR	SSR write pointer register

             {
    SNRT_SSR_REG_STATUS = 0,      
    SNRT_SSR_REG_REPEAT = 1,      
    SNRT_SSR_REG_BOUNDS = 2,      
    SNRT_SSR_REG_STRIDES = 6,     
    SNRT_SSR_REG_IDX_CFG = 10,    
    SNRT_SSR_REG_IDX_BASE = 11,   
    SNRT_SSR_REG_RPTR_INDIR = 16, 
    SNRT_SSR_REG_RPTR = 24,       
    SNRT_SSR_REG_WPTR = 28        
} snrt_ssr_reg_t;

Function Documentation

read_ssr_cfg()

static uint32_t read_ssr_cfg ( const snrt_ssr_reg_t reg, const snrt_ssr_dm_t dm )

inlinestatic

Read the value of an SSR configuration register.

Parameters

reg	The register index.
dm	The SSR index.

Returns

The value of the register.

                                                            {
    uint32_t value;
    asm volatile("scfgri %[value], %[dm] | %[reg]<<5\n"
                 : [ value ] "=r"(value)
                 : [ dm ] "i"(dm), [ reg ] "i"(reg));
    return value;
}

snrt_fpu_fence()

void snrt_fpu_fence ( )

inline

Synchronize the integer and float pipelines.

                             {
    unsigned tmp;
    asm volatile(
        "fmv.x.w %0, fa0\n"
        "mv      %0, %0\n"
        : "+r"(tmp)::"memory");
}

snrt_issr_read()

static void snrt_issr_read ( const snrt_ssr_dm_t dm, volatile void * base, volatile void * idcs, size_t bound, snrt_ssr_idxsize_t idxsize )

inlinestatic

                                                              {
    snrt_issr_set_idx_cfg(dm, idxsize);
    snrt_issr_set_bound(dm, bound);
    snrt_issr_set_ptrs(dm, base, idcs);
}

snrt_issr_set_bound()

static void snrt_issr_set_bound ( const snrt_ssr_dm_t dm, size_t bound )

inlinestatic

                                                                             {
    write_ssr_cfg(SNRT_SSR_REG_BOUNDS, dm, --bound);
}

snrt_issr_set_idx_cfg()

static void snrt_issr_set_idx_cfg ( const snrt_ssr_dm_t dm, snrt_ssr_idxsize_t idxsize )

inlinestatic

Start a streaming indirect read.

Parameters

dm	The SSSR index.
base	The base pointer to the data.
ptr	The pointer to the indirection indices.
bound	The bound of the first (and only) loop.
idxsize	The size of the indices.

                                                                     {
    write_ssr_cfg(SNRT_SSR_REG_IDX_CFG, dm, (idxsize & 0xFF));
}

snrt_issr_set_ptrs()

static void snrt_issr_set_ptrs ( const snrt_ssr_dm_t dm, volatile void * base, volatile void * idcs )

inlinestatic

                                                           {
    write_ssr_cfg(SNRT_SSR_REG_IDX_BASE, dm, (uintptr_t)base);
    write_ssr_cfg(SNRT_SSR_REG_RPTR_INDIR, dm, (uintptr_t)idcs);
}

snrt_sc_disable()

void snrt_sc_disable ( uint32_t mask )

inline

Disable scalar chaining.

                                           {
    asm volatile("csrc 0x7C3, %[mask]\n" : : [ mask ] "r"(mask) :);
}

snrt_sc_enable()

void snrt_sc_enable ( uint32_t mask )

inline

Enable scalar chaining.

Parameters

mask	A bitmask indicating which registers should be enabled for chaining.

                                          {
    asm volatile("csrs 0x7C3, %[mask]\n" : : [ mask ] "r"(mask) :);
}

snrt_ssr_disable()

void snrt_ssr_disable ( )

inline

Disable all SSRs.

                               {
#ifdef __TOOLCHAIN_LLVM__
    __builtin_ssr_disable();
#else
    asm volatile("csrci 0x7C0, 1\n");
#endif
}

snrt_ssr_enable()

void snrt_ssr_enable ( )

inline

Enable all SSRs.

                              {
#ifdef __TOOLCHAIN_LLVM__
    __builtin_ssr_enable();
#else
    asm volatile("csrsi 0x7C0, 1\n");
#endif
}

snrt_ssr_loop_1d()

static void snrt_ssr_loop_1d ( const snrt_ssr_dm_t dm, size_t b0, size_t s0 )

inlinestatic

Configure an SSR data mover for a 1D loop nest.

Parameters

dm	The SSR index.
b0	The bound of the loop.
s0	The stride of the loop.

                                               {
    --b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
}

snrt_ssr_loop_2d()

static void snrt_ssr_loop_2d ( const snrt_ssr_dm_t dm, size_t b0, size_t b1, size_t s0, size_t s1 )

inlinestatic

Configure an SSR data mover for a 2D loop nest.

Parameters

dm	The SSR index.
b0	The bound of the first loop.
b1	The bound of the second loop.
s0	The stride of the first loop.
s1	The stride of the second loop.

                                                                     {
    --b0;
    --b1;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 1), dm, b1);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 1), dm, s1 - a);
    a += s1 * b1;
}

snrt_ssr_loop_3d()

static void snrt_ssr_loop_3d ( const snrt_ssr_dm_t dm, size_t b0, size_t b1, size_t b2, size_t s0, size_t s1, size_t s2 )

inlinestatic

Configure an SSR data mover for a 3D loop nest.

Parameters

dm	The SSR index.
b0	The bound of the first loop.
b1	The bound of the second loop.
b2	The bound of the third loop.
s0	The stride of the first loop.
s1	The stride of the second loop.
s2	The stride of the third loop.

                                               {
    --b0;
    --b1;
    --b2;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 1), dm, b1);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 2), dm, b2);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 1), dm, s1 - a);
    a += s1 * b1;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 2), dm, s2 - a);
    a += s2 * b2;
}

snrt_ssr_loop_4d()

static void snrt_ssr_loop_4d ( const snrt_ssr_dm_t dm, size_t b0, size_t b1, size_t b2, size_t b3, size_t s0, size_t s1, size_t s2, size_t s3 )

inlinestatic

Configure an SSR data mover for a 4D loop nest.

Parameters

dm	The SSR index.
b0	The bound of the first loop.
b1	The bound of the second loop.
b2	The bound of the third loop.
b3	The bound of the fourth loop.
s0	The stride of the first loop.
s1	The stride of the second loop.
s2	The stride of the third loop.
s3	The stride of the fourth loop.

                                                                     {
    --b0;
    --b1;
    --b2;
    --b3;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 1), dm, b1);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 2), dm, b2);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 3), dm, b3);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 1), dm, s1 - a);
    a += s1 * b1;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 2), dm, s2 - a);
    a += s2 * b2;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 3), dm, s3 - a);
    a += s3 * b3;
}

snrt_ssr_read()

static void snrt_ssr_read ( const snrt_ssr_dm_t dm, const snrt_ssr_dim_t dim, volatile void * ptr )

inlinestatic

Start a streaming read.

Parameters

dm	The SSR index.
dim	The number of dimensions to use.
ptr	The pointer to the data.

                                                                               {
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_RPTR + dim), dm,
                  (uintptr_t)ptr);
}

snrt_ssr_repeat()

static void snrt_ssr_repeat ( const snrt_ssr_dm_t dm, size_t count )

inlinestatic

Configure the repetition count for a stream.

Parameters

dm	The SSR index.
count	The repetition count.

                                                                         {
    write_ssr_cfg(SNRT_SSR_REG_REPEAT, dm, count - 1);
}

snrt_ssr_write()

static void snrt_ssr_write ( const snrt_ssr_dm_t dm, const snrt_ssr_dim_t dim, volatile void * ptr )

inlinestatic

Start a streaming write.

Parameters

dm	The SSR index.
dim	The number of dimensions to use.
ptr	The pointer to the data.

                                                      {
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_WPTR + dim), dm,
                  (uintptr_t)ptr);
}

write_ssr_cfg()

static void write_ssr_cfg ( const snrt_ssr_reg_t reg, const snrt_ssr_dm_t dm, uint32_t value )

inlinestatic

Write a value to an SSR configuration register.

Parameters

reg	The register index.
dm	The SSR index.
value	The value to write.

Note

The function passes the reg and dm arguments as an immediate, thus these must be known at compile time. As a consequence, the function must use internal linkage (static keyword) and must be always inlined. This is true also for all functions invoking this function, and passing down their own arguments to reg or dm.

                                                                         {
    asm volatile("scfgwi %[value], %[dm] | %[reg]<<5\n" ::[value] "r"(value),
                 [ dm ] "i"(dm), [ reg ] "i"(reg));
}