ssr.h

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// Copyright 2023 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#pragma once
 
inline void snrt_fpu_fence() {
    unsigned tmp;
    asm volatile(
        "fmv.x.w %0, fa0\n"
        "mv      %0, %0\n"
        : "+r"(tmp)::"memory");
}
 
enum snrt_ssr_dm {
    SNRT_SSR_DM0 = 0,    
    SNRT_SSR_DM1 = 1,    
    SNRT_SSR_DM2 = 2,    
    SNRT_SSR_DM_ALL = 31 
};
 
enum snrt_ssr_dim {
    SNRT_SSR_1D = 0, 
    SNRT_SSR_2D = 1, 
    SNRT_SSR_3D = 2, 
    SNRT_SSR_4D = 3  
};
 
typedef enum snrt_ssr_reg {
    SNRT_SSR_REG_STATUS = 0,      
    SNRT_SSR_REG_REPEAT = 1,      
    SNRT_SSR_REG_BOUNDS = 2,      
    SNRT_SSR_REG_STRIDES = 6,     
    SNRT_SSR_REG_IDX_CFG = 10,    
    SNRT_SSR_REG_IDX_BASE = 11,   
    SNRT_SSR_REG_RPTR_INDIR = 16, 
    SNRT_SSR_REG_RPTR = 24,       
    SNRT_SSR_REG_WPTR = 28        
} snrt_ssr_reg_t;
 
enum snrt_ssr_idxsize {
    SNRT_SSR_IDXSIZE_U8 = 0,  
    SNRT_SSR_IDXSIZE_U16 = 1, 
    SNRT_SSR_IDXSIZE_U32 = 2, 
    SNRT_SSR_IDXSIZE_U64 = 3, 
};
 
inline void snrt_ssr_enable() {
#ifdef __TOOLCHAIN_LLVM__
    __builtin_ssr_enable();
#else
    asm volatile("csrsi 0x7C0, 1\n");
#endif
}
 
inline void snrt_ssr_disable() {
#ifdef __TOOLCHAIN_LLVM__
    __builtin_ssr_disable();
#else
    asm volatile("csrci 0x7C0, 1\n");
#endif
}
 
inline void snrt_sc_enable(uint32_t mask) {
    asm volatile("csrs 0x7C3, %[mask]\n" : : [ mask ] "r"(mask) :);
}
 
inline void snrt_sc_disable(uint32_t mask) {
    asm volatile("csrc 0x7C3, %[mask]\n" : : [ mask ] "r"(mask) :);
}
 
inline uint32_t read_ssr_cfg(enum snrt_ssr_reg reg, uint32_t dm) {
    uint32_t value;
    asm volatile("scfgri %[value], %[dm] | %[reg]<<5\n"
                 : [ value ] "=r"(value)
                 : [ dm ] "i"(dm), [ reg ] "i"(reg));
    return value;
}
 
inline void write_ssr_cfg(enum snrt_ssr_reg reg, uint32_t dm, uint32_t value) {
    asm volatile("scfgwi %[value], %[dm] | %[reg]<<5\n" ::[value] "r"(value),
                 [ dm ] "i"(dm), [ reg ] "i"(reg));
}
 
inline void snrt_ssr_loop_1d(enum snrt_ssr_dm dm, size_t b0, size_t s0) {
    --b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
}
 
inline void snrt_ssr_loop_2d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
                             size_t s0, size_t s1) {
    --b0;
    --b1;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 1), dm, b1);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 1), dm, s1 - a);
    a += s1 * b1;
}
 
inline void snrt_ssr_loop_3d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
                             size_t b2, size_t s0, size_t s1, size_t s2) {
    --b0;
    --b1;
    --b2;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 1), dm, b1);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 2), dm, b2);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 1), dm, s1 - a);
    a += s1 * b1;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 2), dm, s2 - a);
    a += s2 * b2;
}
 
inline void snrt_ssr_loop_4d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
                             size_t b2, size_t b3, size_t s0, size_t s1,
                             size_t s2, size_t s3) {
    --b0;
    --b1;
    --b2;
    --b3;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 0), dm, b0);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 1), dm, b1);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 2), dm, b2);
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_BOUNDS + 3), dm, b3);
    size_t a = 0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 0), dm, s0 - a);
    a += s0 * b0;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 1), dm, s1 - a);
    a += s1 * b1;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 2), dm, s2 - a);
    a += s2 * b2;
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_STRIDES + 3), dm, s3 - a);
    a += s3 * b3;
}
 
inline void snrt_ssr_repeat(enum snrt_ssr_dm dm, size_t count) {
    write_ssr_cfg(SNRT_SSR_REG_REPEAT, dm, count - 1);
}
 
inline void snrt_ssr_read(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim,
                          volatile void *ptr) {
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_RPTR + dim), dm,
                  (uintptr_t)ptr);
}
 
inline void snrt_ssr_write(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim,
                           volatile void *ptr) {
    write_ssr_cfg((snrt_ssr_reg_t)(SNRT_SSR_REG_WPTR + dim), dm,
                  (uintptr_t)ptr);
}
 
inline void snrt_issr_set_idx_cfg(enum snrt_ssr_dm dm,
                                  enum snrt_ssr_idxsize idxsize) {
    write_ssr_cfg(SNRT_SSR_REG_IDX_CFG, dm, (idxsize & 0xFF));
}
 
inline void snrt_issr_set_bound(enum snrt_ssr_dm dm, size_t bound) {
    write_ssr_cfg(SNRT_SSR_REG_BOUNDS, dm, --bound);
}
 
inline void snrt_issr_set_ptrs(enum snrt_ssr_dm dm, volatile void *base,
                               volatile void *idcs) {
    write_ssr_cfg(SNRT_SSR_REG_IDX_BASE, dm, (uintptr_t)base);
    write_ssr_cfg(SNRT_SSR_REG_RPTR_INDIR, dm, (uintptr_t)idcs);
}
 
inline void snrt_issr_read(enum snrt_ssr_dm dm, volatile void *base,
                           volatile void *idcs, size_t bound,
                           enum snrt_ssr_idxsize idxsize) {
    snrt_issr_set_idx_cfg(dm, idxsize);
    snrt_issr_set_bound(dm, bound);
    snrt_issr_set_ptrs(dm, base, idcs);
}