Snitch Runtime
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ssr.h
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1// Copyright 2023 ETH Zurich and University of Bologna.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
21#pragma once
22
26inline void snrt_fpu_fence() {
27 unsigned tmp;
28 asm volatile(
29 "fmv.x.w %0, fa0\n"
30 "mv %0, %0\n"
31 : "+r"(tmp)::"memory");
32}
33
43
53
57enum {
62 REG_RPTR = 24,
63 REG_WPTR = 28
64};
65
69inline void snrt_ssr_enable() {
70#ifdef __TOOLCHAIN_LLVM__
71 __builtin_ssr_enable();
72#else
73 asm volatile("csrsi 0x7C0, 1\n");
74#endif
75}
76
80inline void snrt_ssr_disable() {
81#ifdef __TOOLCHAIN_LLVM__
82 __builtin_ssr_disable();
83#else
84 asm volatile("csrci 0x7C0, 1\n");
85#endif
86}
87
94inline uint32_t read_ssr_cfg(uint32_t reg, uint32_t dm) {
95 uint32_t value;
96 asm volatile("scfgri %[value], %[dm] | %[reg]<<5\n"
97 : [ value ] "=r"(value)
98 : [ dm ] "i"(dm), [ reg ] "i"(reg));
99 return value;
100}
101
108inline void write_ssr_cfg(uint32_t reg, uint32_t dm, uint32_t value) {
109 asm volatile("scfgwi %[value], %[dm] | %[reg]<<5\n" ::[value] "r"(value),
110 [ dm ] "i"(dm), [ reg ] "i"(reg));
111}
112
119inline void snrt_ssr_loop_1d(enum snrt_ssr_dm dm, size_t b0, size_t s0) {
120 --b0;
121 write_ssr_cfg(REG_BOUNDS + 0, dm, b0);
122 size_t a = 0;
123 write_ssr_cfg(REG_STRIDES + 0, dm, s0 - a);
124 a += s0 * b0;
125}
126
135inline void snrt_ssr_loop_2d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
136 size_t s0, size_t s1) {
137 --b0;
138 --b1;
139 write_ssr_cfg(REG_BOUNDS + 0, dm, b0);
140 write_ssr_cfg(REG_BOUNDS + 1, dm, b1);
141 size_t a = 0;
142 write_ssr_cfg(REG_STRIDES + 0, dm, s0 - a);
143 a += s0 * b0;
144 write_ssr_cfg(REG_STRIDES + 1, dm, s1 - a);
145 a += s1 * b1;
146}
147
158inline void snrt_ssr_loop_3d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
159 size_t b2, size_t s0, size_t s1, size_t s2) {
160 --b0;
161 --b1;
162 --b2;
163 write_ssr_cfg(REG_BOUNDS + 0, dm, b0);
164 write_ssr_cfg(REG_BOUNDS + 1, dm, b1);
165 write_ssr_cfg(REG_BOUNDS + 2, dm, b2);
166 size_t a = 0;
167 write_ssr_cfg(REG_STRIDES + 0, dm, s0 - a);
168 a += s0 * b0;
169 write_ssr_cfg(REG_STRIDES + 1, dm, s1 - a);
170 a += s1 * b1;
171 write_ssr_cfg(REG_STRIDES + 2, dm, s2 - a);
172 a += s2 * b2;
173}
174
187inline void snrt_ssr_loop_4d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
188 size_t b2, size_t b3, size_t s0, size_t s1,
189 size_t s2, size_t s3) {
190 --b0;
191 --b1;
192 --b2;
193 --b3;
194 write_ssr_cfg(REG_BOUNDS + 0, dm, b0);
195 write_ssr_cfg(REG_BOUNDS + 1, dm, b1);
196 write_ssr_cfg(REG_BOUNDS + 2, dm, b2);
197 write_ssr_cfg(REG_BOUNDS + 3, dm, b3);
198 size_t a = 0;
199 write_ssr_cfg(REG_STRIDES + 0, dm, s0 - a);
200 a += s0 * b0;
201 write_ssr_cfg(REG_STRIDES + 1, dm, s1 - a);
202 a += s1 * b1;
203 write_ssr_cfg(REG_STRIDES + 2, dm, s2 - a);
204 a += s2 * b2;
205 write_ssr_cfg(REG_STRIDES + 3, dm, s3 - a);
206 a += s3 * b3;
207}
208
214inline void snrt_ssr_repeat(enum snrt_ssr_dm dm, size_t count) {
215 write_ssr_cfg(REG_REPEAT, dm, count - 1);
216}
217
224inline void snrt_ssr_read(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim,
225 volatile void *ptr) {
226 write_ssr_cfg(REG_RPTR + dim, dm, (uintptr_t)ptr);
227}
228
235inline void snrt_ssr_write(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim,
236 volatile void *ptr) {
237 write_ssr_cfg(REG_WPTR + dim, dm, (uintptr_t)ptr);
238}
snrt_ssr_dm
The different SSRs.
Definition ssr.h:37
@ SNRT_SSR_DM0
Definition ssr.h:38
@ SNRT_SSR_DM_ALL
Definition ssr.h:41
@ SNRT_SSR_DM1
Definition ssr.h:39
@ SNRT_SSR_DM2
Definition ssr.h:40
void snrt_ssr_loop_3d(enum snrt_ssr_dm dm, size_t b0, size_t b1, size_t b2, size_t s0, size_t s1, size_t s2)
Configure an SSR data mover for a 3D loop nest.
Definition ssr.h:158
void snrt_ssr_loop_4d(enum snrt_ssr_dm dm, size_t b0, size_t b1, size_t b2, size_t b3, size_t s0, size_t s1, size_t s2, size_t s3)
Configure an SSR data mover for a 4D loop nest.
Definition ssr.h:187
void snrt_ssr_repeat(enum snrt_ssr_dm dm, size_t count)
Configure the repetition count for a stream.
Definition ssr.h:214
uint32_t read_ssr_cfg(uint32_t reg, uint32_t dm)
Read the value of an SSR configuration register.
Definition ssr.h:94
void snrt_ssr_write(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim, volatile void *ptr)
Start a streaming write.
Definition ssr.h:235
void snrt_ssr_enable()
Enable all SSRs.
Definition ssr.h:69
void snrt_ssr_loop_2d(enum snrt_ssr_dm dm, size_t b0, size_t b1, size_t s0, size_t s1)
Configure an SSR data mover for a 2D loop nest.
Definition ssr.h:135
void snrt_ssr_read(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim, volatile void *ptr)
Start a streaming read.
Definition ssr.h:224
void write_ssr_cfg(uint32_t reg, uint32_t dm, uint32_t value)
Write a value to an SSR configuration register.
Definition ssr.h:108
void snrt_ssr_loop_1d(enum snrt_ssr_dm dm, size_t b0, size_t s0)
Configure an SSR data mover for a 1D loop nest.
Definition ssr.h:119
@ REG_REPEAT
Definition ssr.h:59
@ REG_BOUNDS
Definition ssr.h:60
@ REG_WPTR
Definition ssr.h:63
@ REG_RPTR
Definition ssr.h:62
@ REG_STATUS
Definition ssr.h:58
@ REG_STRIDES
Definition ssr.h:61
void snrt_ssr_disable()
Disable all SSRs.
Definition ssr.h:80
void snrt_fpu_fence()
Synchronize the integer and float pipelines.
Definition ssr.h:26
snrt_ssr_dim
The different dimensions.
Definition ssr.h:47
@ SNRT_SSR_2D
Definition ssr.h:49
@ SNRT_SSR_1D
Definition ssr.h:48
@ SNRT_SSR_3D
Definition ssr.h:50
@ SNRT_SSR_4D
Definition ssr.h:51