Snitch Runtime
Loading...
Searching...
No Matches
ssr.h
Go to the documentation of this file.
1// Copyright 2023 ETH Zurich and University of Bologna.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
34#pragma once
35
39inline void snrt_fpu_fence() {
40 unsigned tmp;
41 asm volatile(
42 "fmv.x.w %0, fa0\n"
43 "mv %0, %0\n"
44 : "+r"(tmp)::"memory");
45}
46
56
66
81
91
95inline void snrt_ssr_enable() {
96#ifdef __TOOLCHAIN_LLVM__
97 __builtin_ssr_enable();
98#else
99 asm volatile("csrsi 0x7C0, 1\n");
100#endif
101}
102
106inline void snrt_ssr_disable() {
107#ifdef __TOOLCHAIN_LLVM__
108 __builtin_ssr_disable();
109#else
110 asm volatile("csrci 0x7C0, 1\n");
111#endif
112}
113
119inline void snrt_sc_enable(uint32_t mask) {
120 asm volatile("csrs 0x7C3, %[mask]\n" : : [ mask ] "r"(mask) :);
121}
122
126inline void snrt_sc_disable(uint32_t mask) {
127 asm volatile("csrc 0x7C3, %[mask]\n" : : [ mask ] "r"(mask) :);
128}
129
136inline uint32_t read_ssr_cfg(enum snrt_ssr_reg reg, uint32_t dm) {
137 uint32_t value;
138 asm volatile("scfgri %[value], %[dm] | %[reg]<<5\n"
139 : [ value ] "=r"(value)
140 : [ dm ] "i"(dm), [ reg ] "i"(reg));
141 return value;
142}
143
150inline void write_ssr_cfg(enum snrt_ssr_reg reg, uint32_t dm, uint32_t value) {
151 asm volatile("scfgwi %[value], %[dm] | %[reg]<<5\n" ::[value] "r"(value),
152 [ dm ] "i"(dm), [ reg ] "i"(reg));
153}
154
161inline void snrt_ssr_loop_1d(enum snrt_ssr_dm dm, size_t b0, size_t s0) {
162 --b0;
164 size_t a = 0;
165 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 0, dm, s0 - a);
166 a += s0 * b0;
167}
168
177inline void snrt_ssr_loop_2d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
178 size_t s0, size_t s1) {
179 --b0;
180 --b1;
183 size_t a = 0;
184 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 0, dm, s0 - a);
185 a += s0 * b0;
186 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 1, dm, s1 - a);
187 a += s1 * b1;
188}
189
200inline void snrt_ssr_loop_3d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
201 size_t b2, size_t s0, size_t s1, size_t s2) {
202 --b0;
203 --b1;
204 --b2;
208 size_t a = 0;
209 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 0, dm, s0 - a);
210 a += s0 * b0;
211 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 1, dm, s1 - a);
212 a += s1 * b1;
213 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 2, dm, s2 - a);
214 a += s2 * b2;
215}
216
229inline void snrt_ssr_loop_4d(enum snrt_ssr_dm dm, size_t b0, size_t b1,
230 size_t b2, size_t b3, size_t s0, size_t s1,
231 size_t s2, size_t s3) {
232 --b0;
233 --b1;
234 --b2;
235 --b3;
240 size_t a = 0;
241 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 0, dm, s0 - a);
242 a += s0 * b0;
243 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 1, dm, s1 - a);
244 a += s1 * b1;
245 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 2, dm, s2 - a);
246 a += s2 * b2;
247 write_ssr_cfg(SNRT_SSR_REG_STRIDES + 3, dm, s3 - a);
248 a += s3 * b3;
249}
250
256inline void snrt_ssr_repeat(enum snrt_ssr_dm dm, size_t count) {
257 write_ssr_cfg(SNRT_SSR_REG_REPEAT, dm, count - 1);
258}
259
266inline void snrt_ssr_read(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim,
267 volatile void *ptr) {
268 write_ssr_cfg(SNRT_SSR_REG_RPTR + dim, dm, (uintptr_t)ptr);
269}
270
277inline void snrt_ssr_write(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim,
278 volatile void *ptr) {
279 write_ssr_cfg(SNRT_SSR_REG_WPTR + dim, dm, (uintptr_t)ptr);
280}
281
291 enum snrt_ssr_idxsize idxsize) {
292 write_ssr_cfg(SNRT_SSR_REG_IDX_CFG, dm, (idxsize & 0xFF));
293}
294
295inline void snrt_issr_set_bound(enum snrt_ssr_dm dm, size_t bound) {
297}
298
299inline void snrt_issr_set_ptrs(enum snrt_ssr_dm dm, volatile void *base,
300 volatile void *idcs) {
301 write_ssr_cfg(SNRT_SSR_REG_IDX_BASE, dm, (uintptr_t)base);
302 write_ssr_cfg(SNRT_SSR_REG_RPTR_INDIR, dm, (uintptr_t)idcs);
303}
304
305inline void snrt_issr_read(enum snrt_ssr_dm dm, volatile void *base,
306 volatile void *idcs, size_t bound,
307 enum snrt_ssr_idxsize idxsize) {
308 snrt_issr_set_idx_cfg(dm, idxsize);
309 snrt_issr_set_bound(dm, bound);
310 snrt_issr_set_ptrs(dm, base, idcs);
311}
snrt_ssr_dm
The different SSRs.
Definition ssr.h:50
@ SNRT_SSR_DM0
Definition ssr.h:51
@ SNRT_SSR_DM_ALL
Definition ssr.h:54
@ SNRT_SSR_DM1
Definition ssr.h:52
@ SNRT_SSR_DM2
Definition ssr.h:53
void snrt_ssr_loop_3d(enum snrt_ssr_dm dm, size_t b0, size_t b1, size_t b2, size_t s0, size_t s1, size_t s2)
Configure an SSR data mover for a 3D loop nest.
Definition ssr.h:200
snrt_ssr_reg
The SSR configuration registers.
Definition ssr.h:70
@ SNRT_SSR_REG_IDX_CFG
Definition ssr.h:75
@ SNRT_SSR_REG_RPTR
Definition ssr.h:78
@ SNRT_SSR_REG_WPTR
Definition ssr.h:79
@ SNRT_SSR_REG_BOUNDS
Definition ssr.h:73
@ SNRT_SSR_REG_RPTR_INDIR
Definition ssr.h:77
@ SNRT_SSR_REG_REPEAT
Definition ssr.h:72
@ SNRT_SSR_REG_STATUS
Definition ssr.h:71
@ SNRT_SSR_REG_STRIDES
Definition ssr.h:74
@ SNRT_SSR_REG_IDX_BASE
Definition ssr.h:76
void snrt_ssr_loop_4d(enum snrt_ssr_dm dm, size_t b0, size_t b1, size_t b2, size_t b3, size_t s0, size_t s1, size_t s2, size_t s3)
Configure an SSR data mover for a 4D loop nest.
Definition ssr.h:229
void snrt_sc_disable(uint32_t mask)
Disable scalar chaining.
Definition ssr.h:126
void snrt_ssr_repeat(enum snrt_ssr_dm dm, size_t count)
Configure the repetition count for a stream.
Definition ssr.h:256
uint32_t read_ssr_cfg(enum snrt_ssr_reg reg, uint32_t dm)
Read the value of an SSR configuration register.
Definition ssr.h:136
void write_ssr_cfg(enum snrt_ssr_reg reg, uint32_t dm, uint32_t value)
Write a value to an SSR configuration register.
Definition ssr.h:150
void snrt_issr_set_idx_cfg(enum snrt_ssr_dm dm, enum snrt_ssr_idxsize idxsize)
Start a streaming indirect read.
Definition ssr.h:290
void snrt_ssr_write(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim, volatile void *ptr)
Start a streaming write.
Definition ssr.h:277
void snrt_ssr_enable()
Enable all SSRs.
Definition ssr.h:95
void snrt_ssr_loop_2d(enum snrt_ssr_dm dm, size_t b0, size_t b1, size_t s0, size_t s1)
Configure an SSR data mover for a 2D loop nest.
Definition ssr.h:177
void snrt_ssr_read(enum snrt_ssr_dm dm, enum snrt_ssr_dim dim, volatile void *ptr)
Start a streaming read.
Definition ssr.h:266
void snrt_ssr_loop_1d(enum snrt_ssr_dm dm, size_t b0, size_t s0)
Configure an SSR data mover for a 1D loop nest.
Definition ssr.h:161
void snrt_ssr_disable()
Disable all SSRs.
Definition ssr.h:106
void snrt_sc_enable(uint32_t mask)
Enable scalar chaining.
Definition ssr.h:119
void snrt_fpu_fence()
Synchronize the integer and float pipelines.
Definition ssr.h:39
snrt_ssr_dim
The different dimensions.
Definition ssr.h:60
@ SNRT_SSR_2D
Definition ssr.h:62
@ SNRT_SSR_1D
Definition ssr.h:61
@ SNRT_SSR_3D
Definition ssr.h:63
@ SNRT_SSR_4D
Definition ssr.h:64
snrt_ssr_idxsize
The size of the SSSR indirection indices.
Definition ssr.h:85
@ SNRT_SSR_IDXSIZE_U8
Definition ssr.h:86
@ SNRT_SSR_IDXSIZE_U16
Definition ssr.h:87
@ SNRT_SSR_IDXSIZE_U32
Definition ssr.h:88
@ SNRT_SSR_IDXSIZE_U64
Definition ssr.h:89