Snitch Cluster peripherals
This section documents the registers exposed by the Snitch cluster to interface with various cluster-level peripherals, including the performance counters.
Summary
| Name | Offset | Length | Description |
|---|---|---|---|
snitch_cluster_peripheral.PERF_CNT_EN_0 |
0x0 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_1 |
0x8 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_2 |
0x10 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_3 |
0x18 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_4 |
0x20 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_5 |
0x28 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_6 |
0x30 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_7 |
0x38 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_8 |
0x40 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_9 |
0x48 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_10 |
0x50 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_11 |
0x58 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_12 |
0x60 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_13 |
0x68 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_14 |
0x70 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_EN_15 |
0x78 | 8 | Enable a particular performance counter to start tracking. |
snitch_cluster_peripheral.PERF_CNT_SEL_0 |
0x80 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_1 |
0x88 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_2 |
0x90 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_3 |
0x98 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_4 |
0xa0 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_5 |
0xa8 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_6 |
0xb0 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_7 |
0xb8 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_8 |
0xc0 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_9 |
0xc8 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_10 |
0xd0 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_11 |
0xd8 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_12 |
0xe0 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_13 |
0xe8 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_14 |
0xf0 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_SEL_15 |
0xf8 | 8 | Select the metric that is tracked for each performance counter. |
snitch_cluster_peripheral.PERF_CNT_0 |
0x100 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_1 |
0x108 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_2 |
0x110 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_3 |
0x118 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_4 |
0x120 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_5 |
0x128 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_6 |
0x130 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_7 |
0x138 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_8 |
0x140 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_9 |
0x148 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_10 |
0x150 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_11 |
0x158 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_12 |
0x160 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_13 |
0x168 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_14 |
0x170 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.PERF_CNT_15 |
0x178 | 8 | Performance counter. Set corresponding PERF_CNT_SEL register depending on what |
snitch_cluster_peripheral.SCRATCH_0 |
0x180 | 8 | Scratch registers. Used in the bootrom for various purposes. |
snitch_cluster_peripheral.SCRATCH_1 |
0x188 | 8 | Scratch registers. Used in the bootrom for various purposes. |
snitch_cluster_peripheral.SCRATCH_2 |
0x190 | 8 | Scratch registers. Used in the bootrom for various purposes. |
snitch_cluster_peripheral.SCRATCH_3 |
0x198 | 8 | Scratch registers. Used in the bootrom for various purposes. |
snitch_cluster_peripheral.CL_CLINT_SET |
0x1a0 | 8 | Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt |
snitch_cluster_peripheral.CL_CLINT_CLEAR |
0x1a8 | 8 | Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt |
snitch_cluster_peripheral.ICACHE_PREFETCH_ENABLE |
0x1b0 | 8 | Controls prefetching of the instruction cache. |
PERF_CNT_EN
Enable a particular performance counter to start tracking.
- Reset default: 0x1
- Reset mask: 0x1
Instances
| Name | Offset |
|---|---|
| PERF_CNT_EN_0 | 0x0 |
| PERF_CNT_EN_1 | 0x8 |
| PERF_CNT_EN_2 | 0x10 |
| PERF_CNT_EN_3 | 0x18 |
| PERF_CNT_EN_4 | 0x20 |
| PERF_CNT_EN_5 | 0x28 |
| PERF_CNT_EN_6 | 0x30 |
| PERF_CNT_EN_7 | 0x38 |
| PERF_CNT_EN_8 | 0x40 |
| PERF_CNT_EN_9 | 0x48 |
| PERF_CNT_EN_10 | 0x50 |
| PERF_CNT_EN_11 | 0x58 |
| PERF_CNT_EN_12 | 0x60 |
| PERF_CNT_EN_13 | 0x68 |
| PERF_CNT_EN_14 | 0x70 |
| PERF_CNT_EN_15 | 0x78 |
Fields
{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 63:1 | Reserved | |||
| 0 | rw | 0x1 | ENABLE | Enable a particular performance counter to start tracking. |
PERF_CNT_SEL
Select the metric that is tracked for each performance counter.
- Reset default: 0x0
- Reset mask: 0xffffffff
Instances
| Name | Offset |
|---|---|
| PERF_CNT_SEL_0 | 0x80 |
| PERF_CNT_SEL_1 | 0x88 |
| PERF_CNT_SEL_2 | 0x90 |
| PERF_CNT_SEL_3 | 0x98 |
| PERF_CNT_SEL_4 | 0xa0 |
| PERF_CNT_SEL_5 | 0xa8 |
| PERF_CNT_SEL_6 | 0xb0 |
| PERF_CNT_SEL_7 | 0xb8 |
| PERF_CNT_SEL_8 | 0xc0 |
| PERF_CNT_SEL_9 | 0xc8 |
| PERF_CNT_SEL_10 | 0xd0 |
| PERF_CNT_SEL_11 | 0xd8 |
| PERF_CNT_SEL_12 | 0xe0 |
| PERF_CNT_SEL_13 | 0xe8 |
| PERF_CNT_SEL_14 | 0xf0 |
| PERF_CNT_SEL_15 | 0xf8 |
Fields
{"reg": [{"name": "HART", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "METRIC", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
| Bits | Type | Reset | Name |
|---|---|---|---|
| 63:32 | Reserved | ||
| 31:16 | rw | x | METRIC |
| 15:0 | rw | x | HART |
PERF_CNT_SEL . METRIC
Select the metric that is tracked for each performance counter
| Value | Name | Description |
|---|---|---|
| 0x0000 | CYCLE | Cycle counter. Counts up as long as the cluster is powered. |
| 0x0001 | TCDM_ACCESSED | Increased whenever the TCDM is accessed. Each individual access is tracked, so if n cores access the TCDM, n will be added. Accesses are tracked at the TCDM, so it doesn't matter whether the cores or for example the SSR hardware accesses the TCDM. This is a cluster-global signal. |
| 0x0002 | TCDM_CONGESTED | Incremented whenever an access towards the TCDM is made but the arbitration logic didn't grant the access (due to congestion). It's strictly less than TCDM_ACCESSED. This is a cluster-global signal. |
| 0x0003 | ISSUE_FPU | Operations performed in the FPU. Includes both operations initiated by the sequencer and by the core. When the Xfrep extension is available, this counter is equivalent to ISSUE_FPU_SEQ (see description of ISSUE_FPU_SEQ). If the Xfrep extension is not supported, then it is equivalent to ISSUE_CORE_TO_FPU. This is a hart-local signal. |
| 0x0004 | ISSUE_FPU_SEQ | Incremented whenever the FPU Sequencer issues an FPU instruction. Might not be available if the hardware doesn't support FREP. Note that all FP instructions offloaded by the core to the FPU are routed through the sequencer (although not necessarily buffered) and thus are also counted. The instructions issued independently by the FPU sequencer could thus be calculated as ISSUE_FPU_SEQ_PROPER = ISSUE_FPU_SEQ - ISSUE_CORE_TO_FPU. This is a hart-local signal. |
| 0x0005 | ISSUE_CORE_TO_FPU | Incremented whenever the core issues an FPU instruction. This is a hart-local signal. |
| 0x0006 | RETIRED_INSTR | Instructions retired by the core, both offloaded and not. Does not count instructions issued independently by the FPU sequencer. This is a hart-local signal. |
| 0x0007 | RETIRED_LOAD | Load instructions retired by the core. This is a hart-local signal. |
| 0x0008 | RETIRED_I | Base instructions retired by the core. This is a hart-local signal. |
| 0x0009 | RETIRED_ACC | Offloaded instructions retired by the core. This is a hart-local signal. |
| 0x000a | DMA_AW_STALL | Incremented whenever aw_valid = 1 but aw_ready = 0. This is a DMA-local signal |
| 0x000b | DMA_AR_STALL | Incremented whenever ar_valid = 1 but ar_ready = 0. This is a DMA-local signal |
| 0x000c | DMA_R_STALL | Incremented whenever r_ready = 1 but r_valid = 0. This is a DMA-local signal |
| 0x000d | DMA_W_STALL | Incremented whenever w_valid = 1 but w_ready = 0. This is a DMA-local signal |
| 0x000e | DMA_BUF_W_STALL | Incremented whenever w_ready = 1 but w_valid = 0. This is a DMA-local signal |
| 0x000f | DMA_BUF_R_STALL | Incremented whenever r_valid = 1 but r_ready = 0. This is a DMA-local signal |
| 0x0010 | DMA_AW_DONE | Incremented whenever AW handshake occurs. This is a DMA-local signal |
| 0x0011 | DMA_AW_BW | Whenever AW handshake occurs, the counter is incremented by the number of bytes transfered for this transaction This is a DMA-local signal |
| 0x0012 | DMA_AR_DONE | Incremented whenever AR handshake occurs. This is a DMA-local signal |
| 0x0013 | DMA_AR_BW | Whenever AR handshake occurs, the counter is incremented by the number of bytes transfered for this transaction This is a DMA-local signal |
| 0x0014 | DMA_R_DONE | Incremented whenever R handshake occurs. This is a DMA-local signal |
| 0x0015 | DMA_R_BW | Whenever R handshake occurs, the counter is incremented by the number of bytes transfered in this cycle This is a DMA-local signal |
| 0x0016 | DMA_W_DONE | Incremented whenvever W handshake occurs. This is a DMA-local signal |
| 0x0017 | DMA_W_BW | Whenever W handshake occurs, the counter is incremented by the number of bytes transfered in this cycle This is a DMA-local signal |
| 0x0018 | DMA_B_DONE | Incremented whenever B handshake occurs. This is a DMA-local signal |
| 0x0019 | DMA_BUSY | Incremented whenever DMA is busy. This is a DMA-local signal |
| 0x001a | ICACHE_MISS | Incremented for instruction cache misses. This is a hart-local signal |
| 0x001b | ICACHE_HIT | Incremented for instruction cache hits. This is a hart-local signal |
| 0x001c | ICACHE_PREFETCH | Incremented for instruction cache prefetches. This is a hart-local signal |
| 0x001d | ICACHE_DOUBLE_HIT | Incremented for instruction cache double hit. This is a hart-local signal |
| 0x001e | ICACHE_STALL | Incremented for instruction cache stalls. This is a hart-local signal |
Other values are reserved.
PERF_CNT_SEL . HART
Select from which hart in the cluster, starting from 0,
the event should be counted. For each performance counter
the cores can be selected individually. If a hart greater
than the cluster's total hart size is selected the selection
will wrap and the hart corresponding to hart_select % total_harts_in_cluster
will be selected.
PERF_CNT
Performance counter. Set corresponding PERF_CNT_SEL register depending on what
performance metric and hart you would like to track.
- Reset default: 0x0
- Reset mask: 0xffffffffffff
Instances
| Name | Offset |
|---|---|
| PERF_CNT_0 | 0x100 |
| PERF_CNT_1 | 0x108 |
| PERF_CNT_2 | 0x110 |
| PERF_CNT_3 | 0x118 |
| PERF_CNT_4 | 0x120 |
| PERF_CNT_5 | 0x128 |
| PERF_CNT_6 | 0x130 |
| PERF_CNT_7 | 0x138 |
| PERF_CNT_8 | 0x140 |
| PERF_CNT_9 | 0x148 |
| PERF_CNT_10 | 0x150 |
| PERF_CNT_11 | 0x158 |
| PERF_CNT_12 | 0x160 |
| PERF_CNT_13 | 0x168 |
| PERF_CNT_14 | 0x170 |
| PERF_CNT_15 | 0x178 |
Fields
{"reg": [{"name": "PERF_COUNTER", "bits": 48, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 63:48 | Reserved | |||
| 47:0 | rw | x | PERF_COUNTER | Performance counter |
SCRATCH
Scratch registers. Used in the bootrom for various purposes.
- Reset default: 0x0
- Reset mask: 0xffffffff
Instances
| Name | Offset |
|---|---|
| SCRATCH_0 | 0x180 |
| SCRATCH_1 | 0x188 |
| SCRATCH_2 | 0x190 |
| SCRATCH_3 | 0x198 |
Fields
{"reg": [{"name": "SCRATCH", "bits": 32, "attr": ["rw"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 63:32 | Reserved | |||
| 31:0 | rw | x | SCRATCH | Scratch register |
CL_CLINT_SET
Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt
of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
- Offset: 0x1a0
- Reset default: 0x0
- Reset mask: 0xffffffff
Fields
{"reg": [{"name": "CL_CLINT_SET", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 63:32 | Reserved | |||
| 31:0 | wo | x | CL_CLINT_SET | Set cluster-local interrupt of hart i |
CL_CLINT_CLEAR
Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt
of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID.
- Offset: 0x1a8
- Reset default: 0x0
- Reset mask: 0xffffffff
Fields
{"reg": [{"name": "CL_CLINT_CLEAR", "bits": 32, "attr": ["wo"], "rotate": 0}, {"bits": 32}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 63:32 | Reserved | |||
| 31:0 | wo | x | CL_CLINT_CLEAR | Clear cluster-local interrupt of hart i |
ICACHE_PREFETCH_ENABLE
Controls prefetching of the instruction cache.
- Offset: 0x1b0
- Reset default: 0x1
- Reset mask: 0x1
Fields
{"reg": [{"name": "ICACHE_PREFETCH_ENABLE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 63}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 63:1 | Reserved | |||
| 0 | wo | 0x1 | ICACHE_PREFETCH_ENABLE | Enable instruction prefetching. |