Module axi_iw_converter

Convert between any two AXI ID widths.

Any combination of slave and master port ID width is valid. When the master port ID width is

larger than or equal to the slave port ID width, slave port IDs are simply prepended with zeros

to the width of master port IDs. For reducing the ID width, i.e., when the master port ID

width is smaller than the slave port ID width, there are two options.

Options for reducing the ID width

The two options for reducing ID widths differ in the maximum number of different IDs that can be

in flight at the slave port of this module, given in the AxiSlvPortMaxUniqIds parameter.

Fewer unique slave port IDs than master port IDs

If AxiSlvPortMaxUniqIds <= 2**AxiMstPortIdWidth, there are fewer unique slave port IDs than

master port IDs. Therefore, IDs that are different at the slave port of this module can remain

different at the reduced-ID-width master port and thus remain independently reorderable.

Since the IDs are master port are nonetheless shorter than at the slave port, they need to be

remapped. An instance of axi_id_remap handles this case.

More unique slave port IDs than master port IDs

If AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth, there are more unique slave port IDs than

master port IDs. Therefore, some IDs that are different at the slave port need to be assigned

to the same master port ID and thus become ordered with respect to each other. An instance of

axi_id_serialize handles this case.

ID width of the AXI4+ATOP slave port

ID width of the AXI4+ATOP master port

Maximum number of different IDs that can be in flight at the slave port. Reads and writes are

counted separately (except for ATOPs, which count as both read and write).

It is legal for upstream to have transactions with more unique IDs than the maximum given by

this parameter in flight, but a transaction exceeding the maximum will be stalled until all

transactions of another ID complete.

Maximum number of in-flight transactions with the same ID at the slave port.

This parameter is only relevant if AxiSlvPortMaxUniqIds <= 2**AxiMstPortIdWidth. In that

case, this parameter is passed to [axi_id_remap as AxiMaxTxnsPerId

parameter](module.axi_id_remap#parameter.AxiMaxTxnsPerId).

Maximum number of in-flight transactions at the slave port. Reads and writes are counted

separately (except for ATOPs, which count as both read and write).

This parameter is only relevant if AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth. In that

case, this parameter is passed to

axi_id_serialize.

Maximum number of different IDs that can be in flight at the master port. Reads and writes

are counted separately (except for ATOPs, which count as both read and write).

This parameter is only relevant if AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth. In that

case, this parameter is passed to

axi_id_serialize.

Maximum number of in-flight transactions with the same ID at the master port.

This parameter is only relevant if AxiSlvPortMaxUniqIds > 2**AxiMstPortIdWidth. In that

case, this parameter is passed to

axi_id_serialize.

Address width of both AXI4+ATOP ports

Data width of both AXI4+ATOP ports

User signal width of both AXI4+ATOP ports

Request struct type of the AXI4+ATOP slave port

Response struct type of the AXI4+ATOP slave port

Request struct type of the AXI4+ATOP master port

Response struct type of the AXI4+ATOP master port

Rising-edge clock of both ports

Asynchronous reset, active low

Slave port request

Slave port response

Master port request

Master port response