Simulation flow
=============================================
Phase 1: default config — helloworld
=============================================
[INFO] Restored croc_pkg.sv to default
make: Entering directory '/fosic/designs/croc/sw'
mkdir -p bin
mkdir -p build
mkdir -p build/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c helloworld.c -o build/helloworld.o
mkdir -p build/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c crt0.S -o build/crt0.o
mkdir -p build/lib/src/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c lib/src/clint.c -o build/lib/src/clint.o
mkdir -p build/lib/src/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c lib/src/gpio.c -o build/lib/src/gpio.o
mkdir -p build/lib/src/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c lib/src/idma.c -o build/lib/src/idma.o
mkdir -p build/lib/src/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c lib/src/obi_timer.c -o build/lib/src/obi_timer.o
mkdir -p build/lib/src/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c lib/src/print.c -o build/lib/src/print.o
mkdir -p build/lib/src/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c lib/src/uart.c -o build/lib/src/uart.o
mkdir -p bin/
riscv64-unknown-elf-gcc -o bin/helloworld.elf build/helloworld.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/print_config.c -o build/test/print_config.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/print_config.elf build/test/print_config.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_clint.c -o build/test/test_clint.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_clint.elf build/test/test_clint.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_compute.c -o build/test/test_compute.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_compute.elf build/test/test_compute.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_gpio.c -o build/test/test_gpio.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_gpio.elf build/test/test_gpio.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_idma.c -o build/test/test_idma.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_idma.elf build/test/test_idma.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_interrupts.c -o build/test/test_interrupts.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_interrupts.elf build/test/test_interrupts.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_obi_timer.c -o build/test/test_obi_timer.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_obi_timer.elf build/test/test_obi_timer.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_soc_ctrl.c -o build/test/test_soc_ctrl.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_soc_ctrl.elf build/test/test_soc_ctrl.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p build/test/
riscv64-unknown-elf-gcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Iinclude -Ilib/inc -I/fosic/designs/croc/sw -MMD -MP -c test/test_uart.c -o build/test/test_uart.o
mkdir -p bin/test/
riscv64-unknown-elf-gcc -o bin/test/test_uart.elf build/test/test_uart.o build/crt0.o build/lib/src/clint.o build/lib/src/gpio.o build/lib/src/idma.o build/lib/src/obi_timer.o build/lib/src/print.o build/lib/src/uart.o -static -nostartfiles -lm -lgcc -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding -Tlink.ld
mkdir -p bin/
riscv64-unknown-elf-objdump -D -s bin/helloworld.elf >bin/helloworld.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/print_config.elf >bin/test/print_config.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_clint.elf >bin/test/test_clint.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_compute.elf >bin/test/test_compute.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_gpio.elf >bin/test/test_gpio.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_idma.elf >bin/test/test_idma.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_interrupts.elf >bin/test/test_interrupts.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_obi_timer.elf >bin/test/test_obi_timer.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_soc_ctrl.elf >bin/test/test_soc_ctrl.dump
mkdir -p bin/test/
riscv64-unknown-elf-objdump -D -s bin/test/test_uart.elf >bin/test/test_uart.dump
mkdir -p bin/
riscv64-unknown-elf-objcopy -O verilog bin/helloworld.elf bin/helloworld.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/print_config.elf bin/test/print_config.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_clint.elf bin/test/test_clint.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_compute.elf bin/test/test_compute.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_gpio.elf bin/test/test_gpio.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_idma.elf bin/test/test_idma.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_interrupts.elf bin/test/test_interrupts.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_obi_timer.elf bin/test/test_obi_timer.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_soc_ctrl.elf bin/test/test_soc_ctrl.hex
mkdir -p bin/test/
riscv64-unknown-elf-objcopy -O verilog bin/test/test_uart.elf bin/test/test_uart.hex
make: Leaving directory '/fosic/designs/croc/sw'
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] PDK root: /fosic/designs/croc/technology
[INFO][ENV] Croc PDK: sg13cmos5l
[INFO][ENV] Active technology view: public mirror
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1
[INFO][ENV] Tech LEF: sg13cmos5l_tech.lef
[INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds
[INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib
[INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds
[INFO][Bender] Generate croc_rtl.f
warning: [W03] Ignoring unknown field `pass_targets` in a dependency in manifest for croc_soc.
[INFO][Bender] Remove absolute paths
[INFO][Bender] File list generated: croc_rtl.f
[INFO][Verilator] Build RTL simulation
%Warning-UNSIGNED: ../rtl/common_cells/rr_arb_tree.sv:198:37: Comparison is constant due to unsigned arithmetic
: ... note: In instance 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[4].i_mux.i_rr_arb'
198 | assign upper_mask[i] = (i > rr_q) ? req_d[i] : 1'b0;
| ^
... For warning description see https://verilator.org/warn/UNSIGNED?v=5.042
... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.
%Warning-UNSIGNED: ../rtl/common_cells/rr_arb_tree.sv:199:37: Comparison is constant due to unsigned arithmetic
: ... note: In instance 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[4].i_mux.i_rr_arb'
199 | assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0;
| ^~
%Warning-UNSIGNED: ../rtl/tech_cells_generic/tc_sram.sv:119:36: Comparison is constant due to unsigned arithmetic
: ... note: In instance 'tb_croc_soc.i_croc_soc.i_croc.gen_sram_bank[1].i_sram.i_tc_sram'
119 | for (int unsigned j = 0; j < (Latency-1); j++) begin
| ^
%Warning-UNOPTFLAT: ../rtl/cve2/cve2_id_stage.sv:195:16: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.instr_executing_spec'
195 | logic instr_executing_spec;
| ^~~~~~~~~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.042
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
../rtl/cve2/cve2_id_stage.sv:195:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.instr_executing_spec
../rtl/cve2/cve2_id_stage.sv:713:3: Example path: ALWAYS
../rtl/cve2/cve2_id_stage.sv:240:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.stall_alu
../rtl/cve2/cve2_controller.sv:91:33: Example path: ASSIGNW
../rtl/cve2/cve2_controller.sv:91:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.stall_id_i
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/cve2/cve2_controller.sv:133:9: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.special_req'
133 | logic special_req;
| ^~~~~~~~~~~
../rtl/cve2/cve2_controller.sv:133:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.special_req
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/cve2/cve2_controller.sv:41:33: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.id_in_ready_o'
41 | output logic id_in_ready_o,
| ^~~~~~~~~~~~~
../rtl/cve2/cve2_controller.sv:41:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.id_in_ready_o
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/common_cells/cdc_reset_ctrlr.sv:261:30: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_ack'
261 | logic initiator_phase_transition_ack;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../rtl/common_cells/cdc_reset_ctrlr.sv:261:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_ack
../rtl/common_cells/cdc_reset_ctrlr.sv:265:3: Example path: ALWAYS
../rtl/common_cells/cdc_reset_ctrlr.sv:260:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_req
../rtl/common_cells/cdc_4phase.sv:130:3: Example path: ALWAYS
../rtl/common_cells/cdc_reset_ctrlr.sv:261:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_ack
%Warning-UNOPTFLAT: ../rtl/common_cells/cdc_reset_ctrlr.sv:416:29: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.receiver_phase_ack'
416 | logic receiver_phase_req, receiver_phase_ack;
| ^~~~~~~~~~~~~~~~~~
../rtl/common_cells/cdc_reset_ctrlr.sv:416:29: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.receiver_phase_ack
../rtl/common_cells/cdc_4phase.sv:244:3: Example path: ALWAYS
../rtl/common_cells/cdc_4phase.sv:225:10: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.data_valid
../rtl/common_cells/cdc_reset_ctrlr.sv:446:3: Example path: ALWAYS
../rtl/common_cells/cdc_reset_ctrlr.sv:416:29: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.receiver_phase_ack
%Warning-UNOPTFLAT: ../rtl/riscv-dbg/dm_top.sv:85:37: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack'
85 | logic clear_resumeack;
| ^~~~~~~~~~~~~~~
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:95:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.data_valid
../rtl/riscv-dbg/dm_csrs.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
%Warning-UNOPTFLAT: ../rtl/obi/obi_demux.sv:26:38: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.sbr_port_rsp_o'
26 | output obi_rsp_t sbr_port_rsp_o,
| ^~~~~~~~~~~~~~
../rtl/obi/obi_demux.sv:26:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.sbr_port_rsp_o
../rtl/obi/obi_mux.sv:142:3: Example path: ALWAYS
../rtl/obi/obi_mux.sv:141:39: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.sbr_rsp_r
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/common_cells/delta_counter.sv:22:30: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.i_counter.down_i'
22 | input logic down_i,
| ^~~~~~
../rtl/common_cells/delta_counter.sv:22:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.i_counter.down_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_obi_demux__mgr_ports_req_o
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:95:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.data_valid
../rtl/riscv-dbg/dm_csrs.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/obi/obi_mux.sv:42:47: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellinp__gen_mux[3].i_mux__mgr_port_rsp_i'
42 | input mgr_port_obi_rsp_t mgr_port_rsp_i
| ^~~~~~~~~~~~~~
../rtl/obi/obi_mux.sv:42:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellinp__gen_mux[3].i_mux__mgr_port_rsp_i
../rtl/obi/obi_mux.sv:142:3: Example path: ALWAYS
../rtl/obi/obi_mux.sv:141:39: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[3].i_mux.sbr_rsp_r
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[3].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/obi/obi_demux.sv:29:38: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.mgr_ports_rsp_i'
29 | input obi_rsp_t [NumMgrPorts-1:0] mgr_ports_rsp_i
| ^~~~~~~~~~~~~~~
../rtl/obi/obi_demux.sv:29:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.mgr_ports_rsp_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_obi_demux__mgr_ports_req_o
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:95:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.data_valid
../rtl/riscv-dbg/dm_csrs.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/gpio/gpio.sv:67:9: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_gpio.gpio_intrpt_pending'
67 | logic gpio_intrpt_pending;
| ^~~~~~~~~~~~~~~~~~~
../rtl/gpio/gpio.sv:67:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_gpio.gpio_intrpt_pending
../rtl/croc_domain.sv:60:16: Example path: ASSIGNW
../rtl/cve2/cve2_cs_registers.sv:180:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.cs_registers_i.mip
../rtl/cve2/cve2_controller.sv:66:33: Example path: ASSIGNW
../rtl/cve2/cve2_controller.sv:66:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.irqs_i
../rtl/cve2/cve2_controller.sv:302:3: Example path: ALWAYS
../rtl/cve2/cve2_controller.sv:143:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.mfip_id
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/common_cells/rr_arb_tree.sv:133:33: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d'
133 | logic [NumIn-1:0] req_d;
| ^~~~~
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
%Warning-UNOPTFLAT: ../rtl/obi/obi_demux.sv:41:9: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_user.i_obi_demux.sbr_port_gnt'
41 | logic sbr_port_gnt;
| ^~~~~~~~~~~~
../rtl/obi/obi_demux.sv:41:9: Example path: tb_croc_soc.i_croc_soc.i_user.i_obi_demux.sbr_port_gnt
../rtl/common_cells/rr_arb_tree.sv:107:31: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:107:31: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gnt_i
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_34
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/common_cells/rr_arb_tree.sv:127:33: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]'
127 | logic [2**NumLevels-2:0] gnt_nodes /*verilator split_var*/ ;
| ^~~~~~~~~
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_25
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:259:24: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[1].gen_level[1].sel
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_16
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
make: Entering directory '/fosic/designs/croc/verilator/obj_dir_rtl'
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /foss/tools/verilator/share/verilator/include/verilated.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_dpi.o /foss/tools/verilator/share/verilator/include/verilated_dpi.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_fst_c.o /foss/tools/verilator/share/verilator/include/verilated_fst_c.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /foss/tools/verilator/share/verilator/include/verilated_timing.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /foss/tools/verilator/share/verilator/include/verilated_threads.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.fast.gch
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.slow.gch
echo "" > Vtb_croc_soc__ALL.verilator_deplist.tmp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc.o Vtb_croc_soc.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Dpi_Export__0.o Vtb_croc_soc__Dpi_Export__0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__0.o Vtb_croc_soc___024root__0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__1.o Vtb_croc_soc___024root__1.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__2.o Vtb_croc_soc___024root__2.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__3.o Vtb_croc_soc___024root__3.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__4.o Vtb_croc_soc___024root__4.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__5.o Vtb_croc_soc___024root__5.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__6.o Vtb_croc_soc___024root__6.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__7.o Vtb_croc_soc___024root__7.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__main.o Vtb_croc_soc__main.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Dpi.o Vtb_croc_soc__Dpi.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Trace__0.o Vtb_croc_soc__Trace__0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Trace__1.o Vtb_croc_soc__Trace__1.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__ConstPool_0.o Vtb_croc_soc__ConstPool_0.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__Slow.o Vtb_croc_soc___024root__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__0__Slow.o Vtb_croc_soc___024root__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Syms.o Vtb_croc_soc__Syms.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Trace__0__Slow.o Vtb_croc_soc__Trace__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__TraceDecls__0__Slow.o Vtb_croc_soc__TraceDecls__0__Slow.cpp
g++ -fuse-ld=mold verilated.o verilated_dpi.o verilated_fst_c.o verilated_timing.o verilated_threads.o Vtb_croc_soc__ALL.a -lz -pthread -lpthread -latomic -o Vtb_croc_soc
rm Vtb_croc_soc__ALL.verilator_deplist.tmp
make: Leaving directory '/fosic/designs/croc/verilator/obj_dir_rtl'
- V e r i l a t i o n R e p o r t: Verilator 5.042 2025-11-02 rev v5.042
- Verilator: Built from 112.954 MB sources in 211 modules, into 12.615 MB in 20 C++ files needing 0.003 MB
- Verilator: Walltime 22.077 s (elab=0.093, cvt=1.227, bld=20.539); cpu 1.678 s on 4 threads; alloced 140.086 MB
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] PDK root: /fosic/designs/croc/technology
[INFO][ENV] Croc PDK: sg13cmos5l
[INFO][ENV] Active technology view: public mirror
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1
[INFO][ENV] Tech LEF: sg13cmos5l_tech.lef
[INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds
[INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib
[INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds
[INFO][Verilator] Run RTL simulation
Running program: ../sw/bin/helloworld.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/helloworld.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1401050ns | [CORE] Waking core via CLINT msip
@ 1401050ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1424100ns | [JTAG] Halting hart 0...
@ 1437450ns | [JTAG] Halted
@ 1439750ns | [JTAG] Resumed hart 0
@ 1439750ns | [CORE] Wait for end of code...
@ 3663850ns | [UART] Hello World from Croc!
@ 3663850ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h21, 'ha}
@ 3688800ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 4ms; walltime 1.459 s; speed 1.416 ms/s
- Verilator: cpu 2.604 s on 1 threads; alloced 611 MB
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] PDK root: /fosic/designs/croc/technology
[INFO][ENV] Croc PDK: sg13cmos5l
[INFO][ENV] Active technology view: public mirror
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1
[INFO][ENV] Tech LEF: sg13cmos5l_tech.lef
[INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds
[INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib
[INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds
[INFO][Verilator] Run RTL simulation
Running program: ../sw/bin/test/print_config.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/print_config.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1923150ns | [JTAG] Writing to memory @10000c5c
@ 1930050ns | [CORE] Waking core via CLINT msip
@ 1930050ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1953100ns | [JTAG] Halting hart 0...
@ 1966450ns | [JTAG] Halted
@ 1968750ns | [JTAG] Resumed hart 0
@ 1968750ns | [CORE] Wait for end of code...
@ 4484450ns | [UART] Hello World from Croc v2!
@ 4484450ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h20, 'h76, 'h32, 'h21, 'ha}
@ 6033250ns | [UART] iDMAEnable: 0
@ 6033250ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha}
@ 8162850ns | [UART] Core: CVE2, RV32CIU
@ 8162850ns | [UART] raw: '{'h20, 'h20, 'h43, 'h6f, 'h72, 'h65, 'h3a, 'h20, 'h43, 'h56, 'h45, 'h32, 'h2c, 'h20, 'h52, 'h56, 'h33, 'h32, 'h43, 'h49, 'h55, 'ha}
@ 9614850ns | [UART] PMPEnable: 0
@ 9614850ns | [UART] raw: '{'h20, 'h20, 'h50, 'h4d, 'h50, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha}
@ 12518850ns | [UART] SRAM: 2h banks x 200h words
@ 12518850ns | [UART] raw: '{'h20, 'h20, 'h53, 'h52, 'h41, 'h4d, 'h3a, 'h20, 'h32, 'h68, 'h20, 'h62, 'h61, 'h6e, 'h6b, 'h73, 'h20, 'h78, 'h20, 'h32, 'h30, 'h30, 'h68, 'h20, 'h77, 'h6f, 'h72, 'h64, 'h73, 'ha}
@ 13777250ns | [UART] Peripherals:
@ 13777250ns | [UART] raw: '{'h50, 'h65, 'h72, 'h69, 'h70, 'h68, 'h65, 'h72, 'h61, 'h6c, 'h73, 'h3a, 'ha}
@ 15713250ns | [UART] Debug : present
@ 15713250ns | [UART] raw: '{'h20, 'h20, 'h44, 'h65, 'h62, 'h75, 'h67, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 17649250ns | [UART] Bootrom : present
@ 17649250ns | [UART] raw: '{'h20, 'h20, 'h42, 'h6f, 'h6f, 'h74, 'h72, 'h6f, 'h6d, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 19585250ns | [UART] CLINT : present
@ 19585250ns | [UART] raw: '{'h20, 'h20, 'h43, 'h4c, 'h49, 'h4e, 'h54, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 21521250ns | [UART] SoC Ctrl: present
@ 21521250ns | [UART] raw: '{'h20, 'h20, 'h53, 'h6f, 'h43, 'h20, 'h43, 'h74, 'h72, 'h6c, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 23457250ns | [UART] UART : present
@ 23457250ns | [UART] raw: '{'h20, 'h20, 'h55, 'h41, 'h52, 'h54, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 25393250ns | [UART] GPIO : present
@ 25393250ns | [UART] raw: '{'h20, 'h20, 'h47, 'h50, 'h49, 'h4f, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 27329250ns | [UART] Timer : present
@ 27329250ns | [UART] raw: '{'h20, 'h20, 'h54, 'h69, 'h6d, 'h65, 'h72, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 29652450ns | [UART] iDMA : not present
@ 29652450ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 31975650ns | [UART] User ROM: not present
@ 31975650ns | [UART] raw: '{'h20, 'h20, 'h55, 'h73, 'h65, 'h72, 'h20, 'h52, 'h4f, 'h4d, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 32006650ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 32ms; walltime 15.005 s; speed 1.141 ms/s
- Verilator: cpu 28.052 s on 1 threads; alloced 611 MB
Hello world simulation passed.
=============================================
Phase 2: iDMA enabled — unit tests
=============================================
[INFO] iDMAEnable set to 1'b1
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] PDK root: /fosic/designs/croc/technology
[INFO][ENV] Croc PDK: sg13cmos5l
[INFO][ENV] Active technology view: public mirror
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][ENV] Bender PDK args: -D IHP_SG13CMOS5L=1
[INFO][ENV] Tech LEF: sg13cmos5l_tech.lef
[INFO][ENV] IO LEF/GDS: sg13cmos5l_io.lef/sg13cmos5l_io.gds
[INFO][ENV] IO Liberty tt/ff: sg13cmos5l_io_typ_1p2V_3p3V_25C.lib/sg13cmos5l_io_fast_1p32V_3p6V_m40C.lib
[INFO][ENV] Bondpad LEF/GDS: bondpad5l_70x70.lef/bondpad5l_70x70.gds
[INFO][Bender] Generate croc_rtl.f
warning: [W03] Ignoring unknown field `pass_targets` in a dependency in manifest for croc_soc.
[INFO][Bender] Remove absolute paths
[INFO][Bender] File list generated: croc_rtl.f
[INFO][Verilator] Build RTL simulation
%Warning-UNSIGNED: ../rtl/common_cells/rr_arb_tree.sv:198:37: Comparison is constant due to unsigned arithmetic
: ... note: In instance 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[4].i_mux.i_rr_arb'
198 | assign upper_mask[i] = (i > rr_q) ? req_d[i] : 1'b0;
| ^
... For warning description see https://verilator.org/warn/UNSIGNED?v=5.042
... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.
%Warning-UNSIGNED: ../rtl/common_cells/rr_arb_tree.sv:199:37: Comparison is constant due to unsigned arithmetic
: ... note: In instance 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[4].i_mux.i_rr_arb'
199 | assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0;
| ^~
%Warning-UNSIGNED: ../rtl/tech_cells_generic/tc_sram.sv:119:36: Comparison is constant due to unsigned arithmetic
: ... note: In instance 'tb_croc_soc.i_croc_soc.i_croc.gen_sram_bank[1].i_sram.i_tc_sram'
119 | for (int unsigned j = 0; j < (Latency-1); j++) begin
| ^
%Warning-UNOPTFLAT: ../rtl/cve2/cve2_id_stage.sv:195:16: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.instr_executing_spec'
195 | logic instr_executing_spec;
| ^~~~~~~~~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.042
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
../rtl/cve2/cve2_id_stage.sv:195:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.instr_executing_spec
../rtl/cve2/cve2_id_stage.sv:713:3: Example path: ALWAYS
../rtl/cve2/cve2_id_stage.sv:240:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.stall_alu
../rtl/cve2/cve2_controller.sv:91:33: Example path: ASSIGNW
../rtl/cve2/cve2_controller.sv:91:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.stall_id_i
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/cve2/cve2_controller.sv:133:9: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.special_req'
133 | logic special_req;
| ^~~~~~~~~~~
../rtl/cve2/cve2_controller.sv:133:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.special_req
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/cve2/cve2_controller.sv:41:33: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.id_in_ready_o'
41 | output logic id_in_ready_o,
| ^~~~~~~~~~~~~
../rtl/cve2/cve2_controller.sv:41:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.id_in_ready_o
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/common_cells/cdc_reset_ctrlr.sv:261:30: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_ack'
261 | logic initiator_phase_transition_ack;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../rtl/common_cells/cdc_reset_ctrlr.sv:261:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_ack
../rtl/common_cells/cdc_reset_ctrlr.sv:265:3: Example path: ALWAYS
../rtl/common_cells/cdc_reset_ctrlr.sv:260:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_req
../rtl/common_cells/cdc_4phase.sv:130:3: Example path: ALWAYS
../rtl/common_cells/cdc_reset_ctrlr.sv:261:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.initiator_phase_transition_ack
%Warning-UNOPTFLAT: ../rtl/common_cells/cdc_reset_ctrlr.sv:416:29: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.receiver_phase_ack'
416 | logic receiver_phase_req, receiver_phase_ack;
| ^~~~~~~~~~~~~~~~~~
../rtl/common_cells/cdc_reset_ctrlr.sv:416:29: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.receiver_phase_ack
../rtl/common_cells/cdc_4phase.sv:244:3: Example path: ALWAYS
../rtl/common_cells/cdc_4phase.sv:225:10: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.data_valid
../rtl/common_cells/cdc_reset_ctrlr.sv:446:3: Example path: ALWAYS
../rtl/common_cells/cdc_reset_ctrlr.sv:416:29: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.receiver_phase_ack
%Warning-UNOPTFLAT: ../rtl/riscv-dbg/dm_top.sv:85:37: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack'
85 | logic clear_resumeack;
| ^~~~~~~~~~~~~~~
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:95:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.data_valid
../rtl/riscv-dbg/dm_csrs.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
%Warning-UNOPTFLAT: ../rtl/obi/obi_demux.sv:26:38: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.sbr_port_rsp_o'
26 | output obi_rsp_t sbr_port_rsp_o,
| ^~~~~~~~~~~~~~
../rtl/obi/obi_demux.sv:26:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.sbr_port_rsp_o
../rtl/obi/obi_mux.sv:142:3: Example path: ALWAYS
../rtl/obi/obi_mux.sv:141:39: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.sbr_rsp_r
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/common_cells/delta_counter.sv:22:30: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.i_counter.down_i'
22 | input logic down_i,
| ^~~~~~
../rtl/common_cells/delta_counter.sv:22:30: Example path: tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.i_counter.down_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_obi_demux__mgr_ports_req_o
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:95:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.data_valid
../rtl/riscv-dbg/dm_csrs.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/obi/obi_demux.sv:29:38: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.mgr_ports_rsp_i'
29 | input obi_rsp_t [NumMgrPorts-1:0] mgr_ports_rsp_i
| ^~~~~~~~~~~~~~~
../rtl/obi/obi_demux.sv:29:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_obi_demux.mgr_ports_rsp_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_obi_demux__mgr_ports_req_o
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:95:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.data_valid
../rtl/riscv-dbg/dm_csrs.sv:227:3: Example path: ALWAYS
../rtl/riscv-dbg/dm_top.sv:85:37: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.clear_resumeack
../rtl/riscv-dbg/dm_mem.sv:227:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../rtl/gpio/gpio.sv:67:9: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_gpio.gpio_intrpt_pending'
67 | logic gpio_intrpt_pending;
| ^~~~~~~~~~~~~~~~~~~
../rtl/gpio/gpio.sv:67:9: Example path: tb_croc_soc.i_croc_soc.i_croc.i_gpio.gpio_intrpt_pending
../rtl/croc_domain.sv:60:16: Example path: ASSIGNW
../rtl/cve2/cve2_cs_registers.sv:180:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.cs_registers_i.mip
../rtl/cve2/cve2_controller.sv:66:33: Example path: ASSIGNW
../rtl/cve2/cve2_controller.sv:66:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.irqs_i
../rtl/cve2/cve2_controller.sv:302:3: Example path: ALWAYS
../rtl/cve2/cve2_controller.sv:143:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.id_stage_i.controller_i.mfip_id
../rtl/cve2/cve2_controller.sv:318:3: Example path: ALWAYS
../rtl/cve2/cve2_core.sv:238:16: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.instr_req_int
../rtl/cve2/cve2_prefetch_buffer.sv:118:24: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:45:24: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.valid_new_req
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: ASSIGNW
../rtl/cve2/cve2_prefetch_buffer.sv:32:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.i_core.if_stage_i.prefetch_buffer_i.instr_req_o
../rtl/obi/obi_demux.sv:25:38: Example path: ASSIGNW
../rtl/obi/obi_demux.sv:25:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_demux[3].i_demux.sbr_port_req_i
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[3].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/tech_cells_generic/tc_sram.sv:82:32: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.gen_sram_bank[0].i_sram.__Vcellout__i_tc_sram__rdata_o'
82 | output data_t [NumPorts-1:0] rdata_o
| ^~~~~~~
../rtl/tech_cells_generic/tc_sram.sv:82:32: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_sram_bank[0].i_sram.__Vcellout__i_tc_sram__rdata_o
../rtl/obi/obi_sram_shim.sv:48:23: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:42:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellinp__gen_mux[3].i_mux__mgr_port_rsp_i
../rtl/obi/obi_mux.sv:142:3: Example path: ALWAYS
../rtl/obi/obi_mux.sv:141:39: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[3].i_mux.sbr_rsp_r
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[3].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/obi/obi_demux.sv:41:9: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_user.i_obi_demux.sbr_port_gnt'
41 | logic sbr_port_gnt;
| ^~~~~~~~~~~~
../rtl/obi/obi_demux.sv:41:9: Example path: tb_croc_soc.i_croc_soc.i_user.i_obi_demux.sbr_port_gnt
../rtl/common_cells/rr_arb_tree.sv:107:31: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:107:31: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gnt_i
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_50
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/common_cells/rr_arb_tree.sv:127:33: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]'
127 | logic [2**NumLevels-2:0] gnt_nodes /*verilator split_var*/ ;
| ^~~~~~~~~
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_35
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[1].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../rtl/common_cells/rr_arb_tree.sv:133:33: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d'
133 | logic [NumIn-1:0] req_d;
| ^~~~~
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
../rtl/common_cells/rr_arb_tree.sv:282:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:128:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:285:22: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:247:15: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gen_levels[0].gen_level[0].sel
../rtl/common_cells/rr_arb_tree.sv:293:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[2]
../rtl/common_cells/rr_arb_tree.sv:292:36: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:127:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.gnt_nodes[5]
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:264:85: Example path: __VdfgRegularize_he50b618e_0_20
../rtl/obi/obi_mux.sv:39:47: Example path: ASSIGNW
../rtl/obi/obi_mux.sv:39:47: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.sbr_ports_rsp_o
../rtl/obi/obi_xbar.sv:102:31: Example path: ASSIGNW
../rtl/obi/obi_xbar.sv:59:57: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.sbr_rsps
../rtl/obi/obi_demux.sv:46:3: Example path: ALWAYS
../rtl/obi/obi_demux.sv:28:38: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.__Vcellout__gen_demux[5].i_demux__mgr_ports_req_o
../rtl/common_cells/rr_arb_tree.sv:152:27: Example path: ASSIGNW
../rtl/common_cells/rr_arb_tree.sv:133:33: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[0].i_mux.i_rr_arb.gen_arbiter.req_d
make: Entering directory '/fosic/designs/croc/verilator/obj_dir_rtl'
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /foss/tools/verilator/share/verilator/include/verilated.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_dpi.o /foss/tools/verilator/share/verilator/include/verilated_dpi.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_fst_c.o /foss/tools/verilator/share/verilator/include/verilated_fst_c.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /foss/tools/verilator/share/verilator/include/verilated_timing.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /foss/tools/verilator/share/verilator/include/verilated_threads.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.fast.gch
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.slow.gch
echo "" > Vtb_croc_soc__ALL.verilator_deplist.tmp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc.o Vtb_croc_soc.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Dpi_Export__0.o Vtb_croc_soc__Dpi_Export__0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__0.o Vtb_croc_soc___024root__0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__1.o Vtb_croc_soc___024root__1.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__2.o Vtb_croc_soc___024root__2.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__3.o Vtb_croc_soc___024root__3.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__4.o Vtb_croc_soc___024root__4.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__5.o Vtb_croc_soc___024root__5.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__6.o Vtb_croc_soc___024root__6.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__7.o Vtb_croc_soc___024root__7.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc___024root__8.o Vtb_croc_soc___024root__8.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__main.o Vtb_croc_soc__main.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Dpi.o Vtb_croc_soc__Dpi.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Trace__0.o Vtb_croc_soc__Trace__0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Trace__1.o Vtb_croc_soc__Trace__1.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c -o Vtb_croc_soc__Trace__2.o Vtb_croc_soc__Trace__2.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__ConstPool_0.o Vtb_croc_soc__ConstPool_0.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__Slow.o Vtb_croc_soc___024root__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__0__Slow.o Vtb_croc_soc___024root__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc___024root__1__Slow.o Vtb_croc_soc___024root__1__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Syms.o Vtb_croc_soc__Syms.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Trace__0__Slow.o Vtb_croc_soc__Trace__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__TraceDecls__0__Slow.o Vtb_croc_soc__TraceDecls__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c -o Vtb_croc_soc__Trace__1__Slow.o Vtb_croc_soc__Trace__1__Slow.cpp
g++ -fuse-ld=mold verilated.o verilated_dpi.o verilated_fst_c.o verilated_timing.o verilated_threads.o Vtb_croc_soc__ALL.a -lz -pthread -lpthread -latomic -o Vtb_croc_soc
rm Vtb_croc_soc__ALL.verilator_deplist.tmp
make: Leaving directory '/fosic/designs/croc/verilator/obj_dir_rtl'
- V e r i l a t i o n R e p o r t: Verilator 5.042 2025-11-02 rev v5.042
- Verilator: Built from 112.954 MB sources in 211 modules, into 17.086 MB in 24 C++ files needing 0.004 MB
- Verilator: Walltime 23.145 s (elab=0.098, cvt=1.742, bld=20.951); cpu 2.374 s on 4 threads; alloced 207.094 MB
Found 8 test(s) to run
=========================================
Running test_clint ... PASS
Running test_compute ... PASS
Running test_gpio ... PASS
Running test_idma ... PASS
Running test_interrupts ... PASS
Running test_obi_timer ... PASS
Running test_soc_ctrl ... PASS
Running test_uart ... PASS
=========================================
Summary: 8 passed, 0 failed, 8 total
All tests passed.
=============================================
Simulation completed
=============================================
[INFO] Restored croc_pkg.sv to default
Default: helloworld
Running program: ../sw/bin/helloworld.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/helloworld.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1401050ns | [CORE] Waking core via CLINT msip
@ 1401050ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1424100ns | [JTAG] Halting hart 0...
@ 1437450ns | [JTAG] Halted
@ 1439750ns | [JTAG] Resumed hart 0
@ 1439750ns | [CORE] Wait for end of code...
@ 3663850ns | [UART] Hello World from Croc!
@ 3663850ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h21, 'ha}
@ 3688800ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 4ms; walltime 1.459 s; speed 1.416 ms/s
- Verilator: cpu 2.604 s on 1 threads; alloced 611 MB
Default: print_config
Running program: ../sw/bin/test/print_config.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/print_config.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1923150ns | [JTAG] Writing to memory @10000c5c
@ 1930050ns | [CORE] Waking core via CLINT msip
@ 1930050ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1953100ns | [JTAG] Halting hart 0...
@ 1966450ns | [JTAG] Halted
@ 1968750ns | [JTAG] Resumed hart 0
@ 1968750ns | [CORE] Wait for end of code...
@ 4484450ns | [UART] Hello World from Croc v2!
@ 4484450ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h20, 'h76, 'h32, 'h21, 'ha}
@ 6033250ns | [UART] iDMAEnable: 0
@ 6033250ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha}
@ 8162850ns | [UART] Core: CVE2, RV32CIU
@ 8162850ns | [UART] raw: '{'h20, 'h20, 'h43, 'h6f, 'h72, 'h65, 'h3a, 'h20, 'h43, 'h56, 'h45, 'h32, 'h2c, 'h20, 'h52, 'h56, 'h33, 'h32, 'h43, 'h49, 'h55, 'ha}
@ 9614850ns | [UART] PMPEnable: 0
@ 9614850ns | [UART] raw: '{'h20, 'h20, 'h50, 'h4d, 'h50, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha}
@ 12518850ns | [UART] SRAM: 2h banks x 200h words
@ 12518850ns | [UART] raw: '{'h20, 'h20, 'h53, 'h52, 'h41, 'h4d, 'h3a, 'h20, 'h32, 'h68, 'h20, 'h62, 'h61, 'h6e, 'h6b, 'h73, 'h20, 'h78, 'h20, 'h32, 'h30, 'h30, 'h68, 'h20, 'h77, 'h6f, 'h72, 'h64, 'h73, 'ha}
@ 13777250ns | [UART] Peripherals:
@ 13777250ns | [UART] raw: '{'h50, 'h65, 'h72, 'h69, 'h70, 'h68, 'h65, 'h72, 'h61, 'h6c, 'h73, 'h3a, 'ha}
@ 15713250ns | [UART] Debug : present
@ 15713250ns | [UART] raw: '{'h20, 'h20, 'h44, 'h65, 'h62, 'h75, 'h67, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 17649250ns | [UART] Bootrom : present
@ 17649250ns | [UART] raw: '{'h20, 'h20, 'h42, 'h6f, 'h6f, 'h74, 'h72, 'h6f, 'h6d, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 19585250ns | [UART] CLINT : present
@ 19585250ns | [UART] raw: '{'h20, 'h20, 'h43, 'h4c, 'h49, 'h4e, 'h54, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 21521250ns | [UART] SoC Ctrl: present
@ 21521250ns | [UART] raw: '{'h20, 'h20, 'h53, 'h6f, 'h43, 'h20, 'h43, 'h74, 'h72, 'h6c, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 23457250ns | [UART] UART : present
@ 23457250ns | [UART] raw: '{'h20, 'h20, 'h55, 'h41, 'h52, 'h54, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 25393250ns | [UART] GPIO : present
@ 25393250ns | [UART] raw: '{'h20, 'h20, 'h47, 'h50, 'h49, 'h4f, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 27329250ns | [UART] Timer : present
@ 27329250ns | [UART] raw: '{'h20, 'h20, 'h54, 'h69, 'h6d, 'h65, 'h72, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 29652450ns | [UART] iDMA : not present
@ 29652450ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 31975650ns | [UART] User ROM: not present
@ 31975650ns | [UART] raw: '{'h20, 'h20, 'h55, 'h73, 'h65, 'h72, 'h20, 'h52, 'h4f, 'h4d, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 32006650ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 32ms; walltime 15.005 s; speed 1.141 ms/s
- Verilator: cpu 28.052 s on 1 threads; alloced 611 MB
iDMA: test_clint
Running program: ../sw/bin/test/test_clint.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_clint.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1506850ns | [CORE] Waking core via CLINT msip
@ 1506850ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1529900ns | [JTAG] Halting hart 0...
@ 1543250ns | [JTAG] Halted
@ 1545550ns | [JTAG] Resumed hart 0
@ 1545550ns | [CORE] Wait for end of code...
@ 1646750ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.617 s; speed 1.563 ms/s
- Verilator: cpu 1.054 s on 1 threads; alloced 548 MB
iDMA: test_compute
Running program: ../sw/bin/test/test_compute.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_compute.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1536750ns | [CORE] Waking core via CLINT msip
@ 1536750ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1559800ns | [JTAG] Halting hart 0...
@ 1573150ns | [JTAG] Halted
@ 1575450ns | [JTAG] Resumed hart 0
@ 1575450ns | [CORE] Wait for end of code...
@ 1610050ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.610 s; speed 1.545 ms/s
- Verilator: cpu 1.042 s on 1 threads; alloced 548 MB
iDMA: test_gpio
Running program: ../sw/bin/test/test_gpio.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_gpio.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1541350ns | [CORE] Waking core via CLINT msip
@ 1541350ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1564400ns | [JTAG] Halting hart 0...
@ 1577750ns | [JTAG] Halted
@ 1580050ns | [JTAG] Resumed hart 0
@ 1580050ns | [CORE] Wait for end of code...
@ 1614650ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.681 s; speed 1.479 ms/s
- Verilator: cpu 1.092 s on 1 threads; alloced 548 MB
iDMA: test_idma
Running program: ../sw/bin/test/test_idma.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_idma.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1617250ns | [JTAG] Writing to memory @10000a48
@ 1658650ns | [CORE] Waking core via CLINT msip
@ 1658650ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1681700ns | [JTAG] Halting hart 0...
@ 1695050ns | [JTAG] Halted
@ 1697350ns | [JTAG] Resumed hart 0
@ 1697350ns | [CORE] Wait for end of code...
@ 1731950ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.643 s; speed 1.566 ms/s
- Verilator: cpu 1.106 s on 1 threads; alloced 548 MB
iDMA: test_interrupts
Running program: ../sw/bin/test/test_interrupts.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_interrupts.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1516050ns | [JTAG] Writing to memory @10000998
@ 1525250ns | [CORE] Waking core via CLINT msip
@ 1525250ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1548300ns | [JTAG] Halting hart 0...
@ 1561650ns | [JTAG] Halted
@ 1563950ns | [JTAG] Resumed hart 0
@ 1563950ns | [CORE] Wait for end of code...
@ 1631850ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.625 s; speed 1.538 ms/s
- Verilator: cpu 1.061 s on 1 threads; alloced 548 MB
iDMA: test_obi_timer
Running program: ../sw/bin/test/test_obi_timer.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_obi_timer.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1513750ns | [CORE] Waking core via CLINT msip
@ 1513750ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1536800ns | [JTAG] Halting hart 0...
@ 1550150ns | [JTAG] Halted
@ 1552450ns | [JTAG] Resumed hart 0
@ 1552450ns | [CORE] Wait for end of code...
@ 1620350ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.610 s; speed 1.563 ms/s
- Verilator: cpu 1.036 s on 1 threads; alloced 548 MB
iDMA: test_soc_ctrl
Running program: ../sw/bin/test/test_soc_ctrl.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_soc_ctrl.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1465450ns | [CORE] Waking core via CLINT msip
@ 1465450ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1488500ns | [JTAG] Halting hart 0...
@ 1501850ns | [JTAG] Halted
@ 1504150ns | [JTAG] Resumed hart 0
@ 1504150ns | [CORE] Wait for end of code...
@ 1538750ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.615 s; speed 1.493 ms/s
- Verilator: cpu 1.031 s on 1 threads; alloced 548 MB
iDMA: test_uart
Running program: ../sw/bin/test/test_uart.hex
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42100ns | [JTAG] Initialization success
@ 42100ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94650ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94650ns | [JTAG] Read back correct data
@ 94650ns | [JTAG] Loading binary from ../sw/bin/test/test_uart.hex
@ 96950ns | [JTAG] Writing to memory @10000000
@ 106150ns | [JTAG] Writing to memory @1000000c
@ 119950ns | [JTAG] Writing to memory @10000020
@ 1479250ns | [CORE] Waking core via CLINT msip
@ 1479250ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1502300ns | [JTAG] Halting hart 0...
@ 1515650ns | [JTAG] Halted
@ 1517950ns | [JTAG] Resumed hart 0
@ 1517950ns | [CORE] Wait for end of code...
@ 1818950ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
@ 1818975ns | [UART] TX
- S i m u l a t i o n R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 2ms; walltime 0.909 s; speed 1.301 ms/s
- Verilator: cpu 1.398 s on 1 threads; alloced 548 MB