Simulation flow
=============================================
Phase 1: default config — helloworld
=============================================
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][Bender] Generate croc_netlist_yosys.f
[INFO][Bender] Remove absolute paths
[INFO][Bender] File list generated: croc_netlist_yosys.f
[INFO][Verilator] Build Yosys-netlist simulation
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:67:14: Ignoring unsupported: specify block construct
67 | (A => Y) = 0;
| ^
... For warning description see https://verilator.org/warn/SPECIFYIGN?v=5.052
... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message.
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:85:14: Ignoring unsupported: specify block construct
85 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:103:14: Ignoring unsupported: specify block construct
103 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:121:14: Ignoring unsupported: specify block construct
121 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:142:15: Ignoring unsupported: specify block construct
142 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:164:15: Ignoring unsupported: specify block construct
164 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:183:14: Ignoring unsupported: specify block construct
183 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:202:14: Ignoring unsupported: specify block construct
202 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:221:14: Ignoring unsupported: specify block construct
221 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:241:14: Ignoring unsupported: specify block construct
241 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:297:14: Ignoring unsupported: specify block construct
297 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:332:14: Ignoring unsupported: specify block construct
332 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:367:14: Ignoring unsupported: specify block construct
367 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:397:15: Ignoring unsupported: specify block construct
397 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:445:15: Ignoring unsupported: specify block construct
445 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:491:14: Ignoring unsupported: specify block construct
491 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:526:14: Ignoring unsupported: specify block construct
526 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:567:14: Ignoring unsupported: specify block construct
567 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:610:14: Ignoring unsupported: specify block construct
610 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:653:14: Ignoring unsupported: specify block construct
653 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:694:14: Ignoring unsupported: specify block construct
694 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:733:14: Ignoring unsupported: specify block construct
733 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:765:14: Ignoring unsupported: specify block construct
765 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:798:14: Ignoring unsupported: specify block construct
798 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:831:14: Ignoring unsupported: specify block construct
831 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:870:15: Ignoring unsupported: specify block construct
870 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:946:15: Ignoring unsupported: specify block construct
946 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1022:15: Ignoring unsupported: specify block construct
1022 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1097:15: Ignoring unsupported: specify block construct
1097 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1153:15: Ignoring unsupported: specify block construct
1153 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1209:15: Ignoring unsupported: specify block construct
1209 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1259:15: Ignoring unsupported: specify block construct
1259 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1291:15: Ignoring unsupported: specify block construct
1291 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1326:16: Ignoring unsupported: specify block construct
1326 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1379:16: Ignoring unsupported: specify block construct
1379 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1434:16: Ignoring unsupported: specify block construct
1434 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1489:16: Ignoring unsupported: specify block construct
1489 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1542:16: Ignoring unsupported: specify block construct
1542 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1583:16: Ignoring unsupported: specify block construct
1583 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1625:14: Ignoring unsupported: specify block construct
1625 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1668:14: Ignoring unsupported: specify block construct
1668 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1700:14: Ignoring unsupported: specify block construct
1700 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1717:14: Ignoring unsupported: specify block construct
1717 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1734:14: Ignoring unsupported: specify block construct
1734 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1751:14: Ignoring unsupported: specify block construct
1751 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1768:14: Ignoring unsupported: specify block construct
1768 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1785:14: Ignoring unsupported: specify block construct
1785 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1802:14: Ignoring unsupported: specify block construct
1802 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1819:14: Ignoring unsupported: specify block construct
1819 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1836:14: Ignoring unsupported: specify block construct
1836 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1853:14: Ignoring unsupported: specify block construct
1853 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1870:14: Ignoring unsupported: specify block construct
1870 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1887:14: Ignoring unsupported: specify block construct
1887 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1904:14: Ignoring unsupported: specify block construct
1904 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1946:34: Ignoring unsupported: specify block construct
1946 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2002:34: Ignoring unsupported: specify block construct
2002 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2058:34: Ignoring unsupported: specify block construct
2058 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2114:34: Ignoring unsupported: specify block construct
2114 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2165:34: Ignoring unsupported: specify block construct
2165 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2210:34: Ignoring unsupported: specify block construct
2210 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2255:34: Ignoring unsupported: specify block construct
2255 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2374:32: Ignoring unsupported: specify block construct
2374 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2449:28: Ignoring unsupported: specify block construct
2449 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2491:28: Ignoring unsupported: specify block construct
2491 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2533:28: Ignoring unsupported: specify block construct
2533 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2575:28: Ignoring unsupported: specify block construct
2575 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2617:28: Ignoring unsupported: specify block construct
2617 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2659:28: Ignoring unsupported: specify block construct
2659 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2710:32: Ignoring unsupported: specify block construct
2710 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2778:32: Ignoring unsupported: specify block construct
2778 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2846:32: Ignoring unsupported: specify block construct
2846 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2914:32: Ignoring unsupported: specify block construct
2914 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2994:32: Ignoring unsupported: specify block construct
2994 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3094:32: Ignoring unsupported: specify block construct
3094 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3194:32: Ignoring unsupported: specify block construct
3194 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3294:32: Ignoring unsupported: specify block construct
3294 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3391:32: Ignoring unsupported: specify block construct
3391 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3456:32: Ignoring unsupported: specify block construct
3456 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3521:32: Ignoring unsupported: specify block construct
3521 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3586:32: Ignoring unsupported: specify block construct
3586 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3651:32: Ignoring unsupported: specify block construct
3651 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3716:32: Ignoring unsupported: specify block construct
3716 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3784:32: Ignoring unsupported: specify block construct
3784 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3860:32: Ignoring unsupported: specify block construct
3860 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3936:32: Ignoring unsupported: specify block construct
3936 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4012:32: Ignoring unsupported: specify block construct
4012 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4088:32: Ignoring unsupported: specify block construct
4088 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4164:32: Ignoring unsupported: specify block construct
4164 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4208:14: Ignoring unsupported: specify block construct
4208 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4242:16: Ignoring unsupported: specify block construct
4242 | (A => CO) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4307:15: Ignoring unsupported: specify block construct
4307 | (A => CO) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4333:14: Ignoring unsupported: specify block construct
4333 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4350:14: Ignoring unsupported: specify block construct
4350 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4367:14: Ignoring unsupported: specify block construct
4367 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4384:14: Ignoring unsupported: specify block construct
4384 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4401:14: Ignoring unsupported: specify block construct
4401 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4418:14: Ignoring unsupported: specify block construct
4418 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4435:14: Ignoring unsupported: specify block construct
4435 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4452:14: Ignoring unsupported: specify block construct
4452 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4469:14: Ignoring unsupported: specify block construct
4469 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4486:14: Ignoring unsupported: specify block construct
4486 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4522:14: Ignoring unsupported: specify block construct
4522 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4563:14: Ignoring unsupported: specify block construct
4563 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4604:14: Ignoring unsupported: specify block construct
4604 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4656:14: Ignoring unsupported: specify block construct
4656 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4732:14: Ignoring unsupported: specify block construct
4732 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4808:14: Ignoring unsupported: specify block construct
4808 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4884:14: Ignoring unsupported: specify block construct
4884 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4948:14: Ignoring unsupported: specify block construct
4948 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4988:14: Ignoring unsupported: specify block construct
4988 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5028:14: Ignoring unsupported: specify block construct
5028 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5079:14: Ignoring unsupported: specify block construct
5079 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5154:14: Ignoring unsupported: specify block construct
5154 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5229:14: Ignoring unsupported: specify block construct
5229 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5304:14: Ignoring unsupported: specify block construct
5304 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5360:15: Ignoring unsupported: specify block construct
5360 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5400:15: Ignoring unsupported: specify block construct
5400 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5440:15: Ignoring unsupported: specify block construct
5440 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5476:16: Ignoring unsupported: specify block construct
5476 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5511:16: Ignoring unsupported: specify block construct
5511 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5549:15: Ignoring unsupported: specify block construct
5549 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5596:15: Ignoring unsupported: specify block construct
5596 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5643:15: Ignoring unsupported: specify block construct
5643 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5690:15: Ignoring unsupported: specify block construct
5690 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5737:16: Ignoring unsupported: specify block construct
5737 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5775:16: Ignoring unsupported: specify block construct
5775 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5807:15: Ignoring unsupported: specify block construct
5807 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5828:15: Ignoring unsupported: specify block construct
5828 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5849:15: Ignoring unsupported: specify block construct
5849 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5870:15: Ignoring unsupported: specify block construct
5870 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5891:15: Ignoring unsupported: specify block construct
5891 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5913:14: Ignoring unsupported: specify block construct
5913 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5935:14: Ignoring unsupported: specify block construct
5935 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5957:14: Ignoring unsupported: specify block construct
5957 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5979:14: Ignoring unsupported: specify block construct
5979 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6001:14: Ignoring unsupported: specify block construct
6001 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6023:15: Ignoring unsupported: specify block construct
6023 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6046:15: Ignoring unsupported: specify block construct
6046 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6069:15: Ignoring unsupported: specify block construct
6069 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6093:14: Ignoring unsupported: specify block construct
6093 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6117:14: Ignoring unsupported: specify block construct
6117 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6140:15: Ignoring unsupported: specify block construct
6140 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6164:15: Ignoring unsupported: specify block construct
6164 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6189:15: Ignoring unsupported: specify block construct
6189 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6214:15: Ignoring unsupported: specify block construct
6214 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6241:14: Ignoring unsupported: specify block construct
6241 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6264:15: Ignoring unsupported: specify block construct
6264 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6285:15: Ignoring unsupported: specify block construct
6285 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6307:14: Ignoring unsupported: specify block construct
6307 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6329:14: Ignoring unsupported: specify block construct
6329 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6351:14: Ignoring unsupported: specify block construct
6351 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6373:14: Ignoring unsupported: specify block construct
6373 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6395:15: Ignoring unsupported: specify block construct
6395 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6418:15: Ignoring unsupported: specify block construct
6418 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6441:15: Ignoring unsupported: specify block construct
6441 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6464:15: Ignoring unsupported: specify block construct
6464 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6488:14: Ignoring unsupported: specify block construct
6488 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6512:14: Ignoring unsupported: specify block construct
6512 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6535:15: Ignoring unsupported: specify block construct
6535 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6559:15: Ignoring unsupported: specify block construct
6559 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6584:15: Ignoring unsupported: specify block construct
6584 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6609:15: Ignoring unsupported: specify block construct
6609 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6636:14: Ignoring unsupported: specify block construct
6636 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6663:14: Ignoring unsupported: specify block construct
6663 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6687:14: Ignoring unsupported: specify block construct
6687 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6723:14: Ignoring unsupported: specify block construct
6723 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6759:14: Ignoring unsupported: specify block construct
6759 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6792:14: Ignoring unsupported: specify block construct
6792 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6832:14: Ignoring unsupported: specify block construct
6832 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6871:14: Ignoring unsupported: specify block construct
6871 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6903:14: Ignoring unsupported: specify block construct
6903 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6940:15: Ignoring unsupported: specify block construct
6940 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7014:15: Ignoring unsupported: specify block construct
7014 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7086:15: Ignoring unsupported: specify block construct
7086 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7139:15: Ignoring unsupported: specify block construct
7139 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7190:16: Ignoring unsupported: specify block construct
7190 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7241:16: Ignoring unsupported: specify block construct
7241 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7292:16: Ignoring unsupported: specify block construct
7292 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7343:16: Ignoring unsupported: specify block construct
7343 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7394:16: Ignoring unsupported: specify block construct
7394 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7433:14: Ignoring unsupported: specify block construct
7433 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7473:14: Ignoring unsupported: specify block construct
7473 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7514:14: Ignoring unsupported: specify block construct
7514 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7559:14: Ignoring unsupported: specify block construct
7559 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7595:14: Ignoring unsupported: specify block construct
7595 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7613:14: Ignoring unsupported: specify block construct
7613 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7631:14: Ignoring unsupported: specify block construct
7631 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7652:15: Ignoring unsupported: specify block construct
7652 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7674:15: Ignoring unsupported: specify block construct
7674 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7693:14: Ignoring unsupported: specify block construct
7693 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7712:14: Ignoring unsupported: specify block construct
7712 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7731:14: Ignoring unsupported: specify block construct
7731 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7751:14: Ignoring unsupported: specify block construct
7751 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7771:14: Ignoring unsupported: specify block construct
7771 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7789:14: Ignoring unsupported: specify block construct
7789 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7837:14: Ignoring unsupported: specify block construct
7837 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7855:14: Ignoring unsupported: specify block construct
7855 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7881:15: Ignoring unsupported: specify block construct
7881 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7912:15: Ignoring unsupported: specify block construct
7912 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7947:15: Ignoring unsupported: specify block construct
7947 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8001:15: Ignoring unsupported: specify block construct
8001 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8051:15: Ignoring unsupported: specify block construct
8051 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8082:15: Ignoring unsupported: specify block construct
8082 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8117:15: Ignoring unsupported: specify block construct
8117 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8171:15: Ignoring unsupported: specify block construct
8171 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v:138:54: Ignoring unsupported: specify block construct
138 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:81834:70: Instance has missing pin: 'impl_o'
81834 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram \gen_sram_bank[0].i_sram (
| ^~~~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:201941:143: ... Location of port declaration
201941 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~
... For warning description see https://verilator.org/warn/PINMISSING?v=5.052
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:81855:70: Instance has missing pin: 'impl_o'
81855 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram \gen_sram_bank[1].i_sram (
| ^~~~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:202002:143: ... Location of port declaration
202002 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:81972:53: Instance has missing pin: 'tdo_oe_o'
81972 | \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag i_dmi_jtag (
| ^~~~~~~~~~
../yosys/out/netlist_debug.v:164420:225: ... Location of port declaration
164420 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o);
| ^~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:82713:55: Instance has missing pin: 'overflow_o'
82713 | \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer i_obi_timer (
| ^~~~~~~~~~~
../yosys/out/netlist_debug.v:179706:108: ... Location of port declaration
179706 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o);
| ^~~~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:82748:49: Instance has missing pin: 'irq_no'
82748 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:183788:142: ... Location of port declaration
183788 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:82748:49: Instance has missing pin: 'rts_no'
82748 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:183788:150: ... Location of port declaration
183788 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:82748:49: Instance has missing pin: 'dtr_no'
82748 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:183788:158: ... Location of port declaration
183788 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:82748:49: Instance has missing pin: 'out1_no'
82748 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:183788:166: ... Location of port declaration
183788 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:82748:49: Instance has missing pin: 'out2_no'
82748 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:183788:175: ... Location of port declaration
183788 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:170792:85: Instance has missing pin: 'src_clear_pending_o'
170792 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req \i_dmi_cdc.i_cdc_req (
| ^~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:2403:259: ... Location of port declaration
2403 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:170810:86: Instance has missing pin: 'dst_clear_pending_o'
170810 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp (
| ^~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:2693:201: ... Location of port declaration
2693 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:170810:86: Instance has missing pin: 'src_clear_pending_o'
170810 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp (
| ^~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:2693:260: ... Location of port declaration
2693 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_verification/clk_rst_gen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module clk_rst_gen #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.052
... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message.
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
56 | module tc_sram #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram_impl.sv:27:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
27 | module tc_sram_impl #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module tc_clk_and2 (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
21 | module tc_clk_buffer (
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
31 | module tc_clk_gating #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
56 | module tc_clk_inverter (
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:75:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
75 | module tc_clk_mux2 (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:86:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
86 | module tc_clk_xor2 (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:96:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
96 | module tc_clk_or2 (
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
107 | module tc_clk_delay #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/binary_to_gray.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module binary_to_gray #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter_pkg.sv:14:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | package cb_filter_pkg;
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cc_onehot.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module cc_onehot #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | package cdc_reset_ctrlr_pkg;
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cf_math_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | package cf_math_pkg;
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div.sv:70:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
70 | module clk_int_div #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/credit_counter.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module credit_counter #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/delta_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module delta_counter #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | package ecc_pkg;
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/edge_propagator_tx.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module edge_propagator_tx (
| ^~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/exp_backoff.sv:25:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
25 | module exp_backoff #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/fifo_v3.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module fifo_v3 #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/gray_to_binary.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module gray_to_binary #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/heaviside.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module heaviside #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_4phase_handshake.sv:44:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
44 | module isochronous_4phase_handshake (
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_spill_register.sv:41:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
41 | module isochronous_spill_register #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
24 | module lfsr #(
| ^~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_16bit.sv:23:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
23 | module lfsr_16bit #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_8bit.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module lfsr_8bit #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lossy_valid_to_stream.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
49 | module lossy_valid_to_stream #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/mv_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module mv_filter #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/onehot_to_bin.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module onehot_to_bin #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/plru_tree.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module plru_tree #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/passthrough_stream_fifo.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module passthrough_stream_fifo #(
| ^~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/popcount.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
22 | module popcount #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ring_buffer.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
22 | module ring_buffer #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/rr_arb_tree.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
49 | module rr_arb_tree #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen_bypass.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module rstgen_bypass #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/serial_deglitch.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module serial_deglitch #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module shift_reg #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg_gated.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module shift_reg_gated #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register_flushable.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module spill_register_flushable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_demux.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module stream_demux #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module stream_filter (
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
21 | module stream_fork #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join_dynamic.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module stream_join_dynamic #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_mux.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_mux #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_throttle.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module stream_throttle #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/sub_per_hash.sv:39:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
39 | module sub_per_hash #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/sync.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module sync #(
| ^~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/sync_wedge.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module sync_wedge #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/unread.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module unread (
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module read #(
| ^~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_dync.sv:40:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
40 | module addr_decode_dync #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/boxcar.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module boxcar #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:43:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
43 | module cdc_2phase #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
92 | module cdc_2phase_src #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
142 | module cdc_2phase_dst #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:36:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
36 | module cdc_4phase #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
92 | module cdc_4phase_src #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:205:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
205 | module cdc_4phase_dst #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div_static.sv:60:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
60 | module clk_int_div_static #(
| ^~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/trip_counter.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module trip_counter #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode.sv:35:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
35 | module addr_decode #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_napot.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module addr_decode_napot #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/multiaddr_decode.sv:32:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
32 | module multiaddr_decode #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:45:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
45 | module cb_filter #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
203 | module hash_block #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_2phase.sv:47:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
47 | module cdc_fifo_2phase #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
73 | module clk_mux_glitch_free #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:256:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
256 | module clk_or_tree #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/counter.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module counter #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_decode.sv:29:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
29 | module ecc_decode import ecc_pkg::*; #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_encode.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
22 | module ecc_encode import ecc_pkg::*; #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/edge_detect.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module edge_detect (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lzc.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module lzc #(
| ^~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/max_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module max_counter #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module rstgen (
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module spill_register #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_delay.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module stream_delay #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module stream_fifo #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork_dynamic.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
24 | module stream_fork_dynamic #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module stream_join #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
109 | module cdc_reset_ctrlr
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:187:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
187 | module cdc_reset_ctrlr_half
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
103 | module cdc_fifo_gray #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:171:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
171 | module cdc_fifo_gray_src #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:231:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
231 | module cdc_fifo_gray_dst #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/fall_through_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module fall_through_register #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/id_queue.sv:50:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
50 | module id_queue #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_to_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module stream_to_mem #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter_flushable.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_arbiter_flushable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo_optimal_wrap.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module stream_fifo_optimal_wrap #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_register #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_xbar.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module stream_xbar #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
103 | module cdc_fifo_gray_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
268 | module cdc_fifo_gray_src_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
328 | module cdc_fifo_gray_dst_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:54:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
54 | module cdc_2phase_clearable #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199 | module cdc_2phase_src_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:269:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
269 | module cdc_2phase_dst_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks_detailed.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module mem_to_banks_detailed #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_arbiter #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_omega_net.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module stream_omega_net #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module mem_to_banks #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_pkg.sv:7:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | package obi_pkg;
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_rready_converter.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_rready_converter #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/apb_to_obi.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module apb_to_obi #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_to_apb.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module obi_to_apb #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_atop_resolver
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:536:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
536 | module obi_atop_resolver_intf
| ^~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_cut.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_cut #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_demux #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:114:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
114 | module obi_demux_intf #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_err_sbr #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:69:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
69 | module obi_err_sbr_intf #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module obi_mux #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:166:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
166 | module obi_mux_intf #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_sram_shim.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_sram_shim #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:8:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | module obi_xbar #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
161 | module obi_xbar_intf #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/apb/apb_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | package apb_pkg;
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | package cve2_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_alu.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module cve2_alu #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_branch_predict.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
21 | module cve2_branch_predict (
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_compressed_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module cve2_compressed_decoder (
| ^~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_controller.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module cve2_controller #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_counter.sv:6:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
6 | module cve2_counter #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_csr.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module cve2_csr #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module cve2_decoder #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_fetch_fifo.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_fetch_fifo #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_load_store_unit.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module cve2_load_store_unit
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_fast.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module cve2_multdiv_fast #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_slow.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module cve2_multdiv_slow
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pmp.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module cve2_pmp #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_register_file_ff.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module cve2_register_file_ff #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_wb.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module cve2_wb #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_cs_registers.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_cs_registers #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_ex_block.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module cve2_ex_block #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_id_stage.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module cve2_id_stage #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_prefetch_buffer.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module cve2_prefetch_buffer #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_if_stage.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_if_stage import cve2_pkg::*; (
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_core.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_core import cve2_pkg::*; #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_pkg.sv:11:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | package idma_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_channel_coupler.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module idma_channel_coupler #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_dataflow_element.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module idma_dataflow_element #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module idma_obi_read #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_write.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module idma_obi_write #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module idma_nd_midend #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
252 | module idma_nd_counter #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_transfer_id_gen.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module idma_transfer_id_gen #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_page_splitter.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module idma_legalizer_page_splitter #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_transport_layer_rw_obi.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module idma_transport_layer_rw_obi #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_rw_obi.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module idma_legalizer_rw_obi #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_backend_rw_obi.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module idma_backend_rw_obi #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/croc_idma.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module croc_idma #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | package obi_uart_pkg;
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_baudgen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_uart_baudgen import obi_uart_pkg::*; #()
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_interrupts.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_uart_interrupts import obi_uart_pkg::*; #()
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_modem.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_uart_modem import obi_uart_pkg::*; #()
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_rx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart_rx import obi_uart_pkg::*; #()
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_tx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart_tx #()
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_register.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart_register import obi_uart_pkg::*; #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_pkg.sv:19:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | package dm;
| ^~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module debug_rom (
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module debug_rom_one_scratch (
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_csrs.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module dm_csrs #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dm_mem #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_cdc.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dmi_cdc (
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag_tap.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dmi_jtag_tap #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_sba.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module dm_sba #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_top.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module dm_top #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dmi_jtag #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_obi_top.sv:63:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
63 | module dm_obi_top #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module jtag_driver_simple #(
| ^~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:163:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
163 | module riscv_dbg_simple #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/croc_pkg.sv:12:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | package croc_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/user_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | package user_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/soc_ctrl/soc_ctrl_regs_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | package soc_ctrl_regs_pkg;
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/gpio/gpio_reg_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | package gpio_reg_pkg;
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/clint/clint_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | package clint_reg_pkg;
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_timer/obi_timer_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | package obi_timer_reg_pkg;
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:4:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
4 | module \bootrom$croc_chip.i_croc_soc.i_croc.i_bootrom (clk_i, rst_ni, obi_req_i, obi_rsp_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2403:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
2403 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2693:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
2693 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2962:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
2962 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst (clk_i, rst_ni, data_o, clear_i, ready_i, valid_o, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:5846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
5846 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst (clk_i, rst_ni, data_o, clear_i, ready_i, valid_o, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8256:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8256 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src (clk_i, rst_ni, data_i, clear_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9419 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src (clk_i, rst_ni, data_i, clear_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10402 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10530 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10658:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10658 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10786:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10786 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, ready_i, valid_o, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10914 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11112:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11112 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11310:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11310 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11508:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11508 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11706:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11706 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11814:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11814 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11922:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11922 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:12470:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12470 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:13018:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13018 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:13566:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13566 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:14114:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14114 | module \clint$croc_chip.i_croc_soc.i_croc.i_clint (clk_i, rst_ni, obi_req_i, obi_rsp_o, rtc_i, software_irq_o, timer_irq_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:19568:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19568 | module \core_wrap$croc_chip.i_croc_soc.i_croc.i_core_wrap (clk_i, rst_ni, core_busy_o, test_enable_i, irqs_i, timer_irq_i, software_irq_i, boot_addr_i, instr_req_o, instr_gnt_i, instr_rvalid_i, instr_addr_o, instr_rdata_i, instr_err_i, data_req_o, data_gnt_i, data_rvalid_i, data_we_o, data_be_o, data_addr_o, data_wdata_o
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:54290:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
54290 | module croc_chip(clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio0_io, gpio1_io, gpio2_io, gpio3_io, gpio4_io, gpio5_io, gpio6_io, gpio7_io, gpio8_io
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:55120:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
55120 | module \croc_domain$croc_chip.i_croc_soc.i_croc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, user_sbr_obi_req_o, user_sbr_obi_rsp_i, user_mgr_obi_req_i, user_mgr_obi_rsp_o, interrupts_i, core_busy_o
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:82780:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
82780 | module \croc_soc$croc_chip.i_croc_soc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio_i, gpio_o, gpio_out_en_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:83455:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
83455 | module \cve2_cs_registers$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.cs_registers_i (clk_i, rst_ni, boot_addr_i, hart_id_i, irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_pending_o, pc_id_i, priv_mode_id_o, priv_mode_lsu_o, csr_mstatus_tw_o, csr_mtvec_o, csr_mtvec_init_i, csr_access_i, csr_addr_i, csr_wdata_i, csr_op_i, csr_op_en_i, csr_rdata_o
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:105166:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
105166 | module \cve2_register_file_ff$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.register_file_i (clk_i, rst_ni, test_en_i, raddr_a_i, rdata_a_o, raddr_b_i, rdata_b_o, waddr_a_i, wdata_a_i, we_a_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:135215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
135215 | module \dm_top$croc_chip.i_croc_soc.i_croc.i_dm_top.i_dm_top (clk_i, rst_ni, testmode_i, debug_req_o, unavailable_i, hartinfo_i, slave_req_i, slave_we_i, slave_addr_i, slave_be_i, slave_wdata_i, slave_rdata_o, master_req_o, master_we_o, master_wdata_o, master_be_o, master_gnt_i, dmi_rst_ni, dmi_req_valid_i, dmi_req_ready_o, dmi_req_i
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:164420:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
164420 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:171221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
171221 | module \gpio$croc_chip.i_croc_soc.i_croc.i_gpio (clk_i, rst_ni, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, obi_req_i, obi_rsp_o, interrupt_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:179706:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
179706 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:183788:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
183788 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, obi_req_i, obi_rsp_o, irq_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:197807:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
197807 | module \soc_ctrl_regs$croc_chip.i_croc_soc.i_croc.i_soc_ctrl (clk_i, rst_ni, obi_req_i, obi_rsp_o, fetch_en_o, sram_dly_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:199830:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199830 | module \sync$croc_chip.i_croc_soc.i_croc.i_clint.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:199869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199869 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:199908:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199908 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:199947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199947 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:199986:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199986 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200025:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200025 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200075:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200075 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200125 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200164:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200164 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200203 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200242:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200242 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200281:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200281 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200331:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200331 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200381 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[0].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200420:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200420 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[10].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200459 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[11].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200498:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200498 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[12].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200537:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200537 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[13].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200576:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200576 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[14].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200615:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200615 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[15].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200654:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200654 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[16].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200693:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200693 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[17].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200732 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[18].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200771:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200771 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[19].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200810:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200810 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[1].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200849:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200849 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[20].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200888:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200888 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[21].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200927:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200927 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[22].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:200966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
200966 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[23].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201005:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201005 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[24].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201044:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201044 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[25].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201083:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201083 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[26].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201122 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[27].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201161 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[28].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201200:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201200 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[29].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201239:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201239 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[2].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201278:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201278 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[30].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201317:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201317 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[31].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201356:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201356 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[3].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201395:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201395 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[4].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201434 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[5].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201473:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201473 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[6].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201512:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201512 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[7].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201551 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[8].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201590:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201590 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[9].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201629:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201629 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cd (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201668:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201668 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cts (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201707 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_dsr (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201746:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201746 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_ri (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201785 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_rx.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201824 | module \tc_clk_inverter$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_tck_inv (clk_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201841:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201841 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_dft_tck_mux (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201866:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201866 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_init_no (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201891 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_n (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201916:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201916 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_no (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:201941:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
201941 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:202002:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
202002 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:202063:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
202063 | module \user_domain$croc_chip.i_croc_soc.i_user (clk_i, rst_ni, ref_clk_i, testmode_i, user_sbr_obi_req_i, user_sbr_obi_rsp_o, user_mgr_obi_req_o, user_mgr_obi_rsp_i, gpio_in_sync_i, interrupts_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/test/tb_croc_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | package tb_croc_pkg;
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/test/croc_vip.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module croc_vip #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/test/tb_croc_soc.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module tb_croc_soc #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:55731:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2116'
55731 | wire \$abc$162018$new_n2116 ;
| ^~~~~~~~~~~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.052
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
../yosys/out/netlist_debug.v:55731:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2116
../ihp13/pdk/verilog/ez130_8t.v:6899:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55402:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n1787
../ihp13/pdk/verilog/ez130_8t.v:6719:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55569:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n1954
../ihp13/pdk/verilog/ez130_8t.v:4329:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55654:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2039
../ihp13/pdk/verilog/ez130_8t.v:5908:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$165516.A__bar
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_1648
../ihp13/pdk/verilog/ez130_8t.v:6113:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6113:23: Example path: __VdfgRegularize_h6e95ff9d_0_75
../ihp13/pdk/verilog/ez130_8t.v:6303:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:58560:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_416_
../yosys/out/netlist_debug.v:82754:22: Example path: ASSIGNW
../yosys/out/netlist_debug.v:82754:22: Example path: __VdfgRegularize_h6e95ff9d_0_1016
../yosys/out/netlist_debug.v:197803:47: Example path: ASSIGNW
../yosys/out/netlist_debug.v:183799:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:1199:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:1192:23: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$162066.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_1616
../ihp13/pdk/verilog/ez130_8t.v:4329:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:57877:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n5156
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: __VdfgRegularize_h6e95ff9d_0_1617
../ihp13/pdk/verilog/ez130_8t.v:5908:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:7009:20: Signal unoptimizable: Circular combinational logic: '__VdfgRegularize_h6e95ff9d_0_1632'
7009 | or (Y, int_fwire_1, int_fwire_0, E__bar);
| ^
../ihp13/pdk/verilog/ez130_8t.v:7009:20: Example path: __VdfgRegularize_h6e95ff9d_0_1632
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55776:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2165
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_520
../ihp13/pdk/verilog/ez130_8t.v:6484:16: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6484:16: Example path: __VdfgRegularize_h6e95ff9d_0_1578
../ihp13/pdk/verilog/ez130_8t.v:6867:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:60829:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55839:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2239
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: __VdfgRegularize_h6e95ff9d_0_528
../ihp13/pdk/verilog/ez130_8t.v:6260:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:56772:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n3360
../ihp13/pdk/verilog/ez130_8t.v:1614:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:1611:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$163914.D__bar
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:202112:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$178332$new_n108
../yosys/out/netlist_debug.v:202627:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:202080:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$157591$auto$blifparse.cc:397:parse_blif$160133.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6260:12: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6260:12: Example path: __VdfgRegularize_h6e95ff9d_0_1631
../ihp13/pdk/verilog/ez130_8t.v:7009:20: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:7009:20: Example path: __VdfgRegularize_h6e95ff9d_0_1632
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:6089:15: Signal unoptimizable: Circular combinational logic: '__VdfgRegularize_h6e95ff9d_0_1616'
6089 | or (Y, A__bar, B__bar, C__bar);
| ^
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_1616
../ihp13/pdk/verilog/ez130_8t.v:4329:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:57877:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n5156
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: __VdfgRegularize_h6e95ff9d_0_1617
../ihp13/pdk/verilog/ez130_8t.v:5908:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$165516.A__bar
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_1648
../ihp13/pdk/verilog/ez130_8t.v:6113:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6113:23: Example path: __VdfgRegularize_h6e95ff9d_0_75
../ihp13/pdk/verilog/ez130_8t.v:6303:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:58560:8: Example path: tb_croc_soc.i_croc_soc.i_croc.all_periph_obi_req_416_
../yosys/out/netlist_debug.v:82754:22: Example path: ASSIGNW
../yosys/out/netlist_debug.v:82754:22: Example path: __VdfgRegularize_h6e95ff9d_0_1016
../yosys/out/netlist_debug.v:197803:47: Example path: ASSIGNW
../yosys/out/netlist_debug.v:183799:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:1199:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:1192:23: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$162066.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_1616
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:363:20: Signal unoptimizable: Circular combinational logic: '__VdfgRegularize_h6e95ff9d_0_470'
363 | or (Y, int_fwire_0, C);
| ^
../ihp13/pdk/verilog/ez130_8t.v:363:20: Example path: __VdfgRegularize_h6e95ff9d_0_470
../ihp13/pdk/verilog/ez130_8t.v:1619:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:1610:7: Example path: tb_croc_soc.i_croc_soc.i_croc.i_dm_top.i_dm_top.$abc$171203$auto$blifparse.cc:397:parse_blif$173902.A__bar
../ihp13/pdk/verilog/ez130_8t.v:5802:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5800:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$162288.B__bar
../ihp13/pdk/verilog/ez130_8t.v:5803:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55759:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2146
../ihp13/pdk/verilog/ez130_8t.v:7609:10: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:7609:10: Example path: __VdfgRegularize_h6e95ff9d_0_474
../ihp13/pdk/verilog/ez130_8t.v:6484:24: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6484:24: Example path: __VdfgRegularize_h6e95ff9d_0_523
../ihp13/pdk/verilog/ez130_8t.v:6755:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55832:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2230
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:56346:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2818
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:56349:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2821
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:202112:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$178332$new_n108
../yosys/out/netlist_debug.v:202627:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:202080:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$157591$auto$blifparse.cc:397:parse_blif$160133.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6260:12: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6260:12: Example path: __VdfgRegularize_h6e95ff9d_0_1631
../ihp13/pdk/verilog/ez130_8t.v:7009:20: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:7009:20: Example path: __VdfgRegularize_h6e95ff9d_0_1632
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55776:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2165
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:15: Example path: __VdfgRegularize_h6e95ff9d_0_520
../ihp13/pdk/verilog/ez130_8t.v:6484:16: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6484:16: Example path: __VdfgRegularize_h6e95ff9d_0_1578
../ihp13/pdk/verilog/ez130_8t.v:6867:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:60829:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55839:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n2239
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:63:11: Example path: __VdfgRegularize_h6e95ff9d_0_528
../ihp13/pdk/verilog/ez130_8t.v:6260:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:56772:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$new_n3360
../ihp13/pdk/verilog/ez130_8t.v:1614:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:1611:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$162018$auto$blifparse.cc:397:parse_blif$163914.D__bar
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
make: Entering directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys'
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /foss/tools/verilator/share/verilator/include/verilated.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_dpi.o /foss/tools/verilator/share/verilator/include/verilated_dpi.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /foss/tools/verilator/share/verilator/include/verilated_timing.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /foss/tools/verilator/share/verilator/include/verilated_threads.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.fast.gch
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.slow.gch
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_1.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_2.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_3.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc__Dpi.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc__ConstPool__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__1__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__2__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__3__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc__Syms__Slow.cpp
g++ -fuse-ld=mold verilated.o verilated_dpi.o verilated_timing.o verilated_threads.o Vtb_croc_soc__ALL.a -pthread -lpthread -latomic -o Vtb_croc_soc
rm Vtb_croc_soc__ALL.verilator_deplist.tmp
make: Leaving directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys'
- V e r i l a t i o n R e p o r t: Verilator 5.052 2026-09-05 rev v5.052
- Verilator: Built from 193.085 MB sources in 528 modules, into 26.790 MB in 24 C++ files needing 0.039 MB
- Verilator: Walltime 69.540 s (elab=1.129, cvt=10.073, bld=56.897); cpu 12.971 s on 4 threads; allocated 880.551 MB
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][Verilator] Run Yosys-netlist simulation
Running program: ../sw/bin/helloworld.hex
-Info: ../rtl/test/tb_croc_soc.sv:167: $dumpvar ignored, as Verilated without --trace
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42050ns | [JTAG] Initialization success
@ 42050ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94600ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94600ns | [JTAG] Read back correct data
@ 94600ns | [JTAG] Loading binary from ../sw/bin/helloworld.hex
@ 96900ns | [JTAG] Writing to memory @10000000
@ 106100ns | [JTAG] Writing to memory @1000000c
@ 119900ns | [JTAG] Writing to memory @10000020
@ 1412500ns | [CORE] Waking core via CLINT msip
@ 1412500ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1435550ns | [JTAG] Halting hart 0...
@ 1448900ns | [JTAG] Halted
@ 1451200ns | [JTAG] Resumed hart 0
@ 1451200ns | [CORE] Wait for end of code...
@ 3675300ns | [UART] Hello World from Croc!
@ 3675300ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h21, 'ha}
@ 3700250ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 4ms; walltime 1.279 s; speed 2.893 ms/s
- Verilator: cpu 1.279 s on 1 threads; allocated 6 MB
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][Verilator] Run Yosys-netlist simulation
Running program: ../sw/bin/test/print_config.hex
-Info: ../rtl/test/tb_croc_soc.sv:167: $dumpvar ignored, as Verilated without --trace
ClkFrequency: 20MHz
UartRealBaudRate: 113636
@ 42050ns | [JTAG] Initialization success
@ 42050ns | [JTAG] Writing 0x12345678 to 0x10000000
@ 94600ns | [JTAG] Read 0x12345678 from 0x10000000
@ 94600ns | [JTAG] Read back correct data
@ 94600ns | [JTAG] Loading binary from ../sw/bin/test/print_config.hex
@ 96900ns | [JTAG] Writing to memory @10000000
@ 106100ns | [JTAG] Writing to memory @1000000c
@ 119900ns | [JTAG] Writing to memory @10000020
@ 1932300ns | [JTAG] Writing to memory @10000c6c
@ 1939200ns | [CORE] Waking core via CLINT msip
@ 1939200ns | [JTAG] Writing 0x00000001 to 0x02040000
@ 1962250ns | [JTAG] Halting hart 0...
@ 1975600ns | [JTAG] Halted
@ 1977900ns | [JTAG] Resumed hart 0
@ 1977900ns | [CORE] Wait for end of code...
@ 4493600ns | [UART] Hello World from Croc v2!
@ 4493600ns | [UART] raw: '{'h48, 'h65, 'h6c, 'h6c, 'h6f, 'h20, 'h57, 'h6f, 'h72, 'h6c, 'h64, 'h20, 'h66, 'h72, 'h6f, 'h6d, 'h20, 'h43, 'h72, 'h6f, 'h63, 'h20, 'h76, 'h32, 'h21, 'ha}
@ 6042400ns | [UART] iDMAEnable: 0
@ 6042400ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha}
@ 8172000ns | [UART] Core: CVE2, RV32CIU
@ 8172000ns | [UART] raw: '{'h20, 'h20, 'h43, 'h6f, 'h72, 'h65, 'h3a, 'h20, 'h43, 'h56, 'h45, 'h32, 'h2c, 'h20, 'h52, 'h56, 'h33, 'h32, 'h43, 'h49, 'h55, 'ha}
@ 9624000ns | [UART] PMPEnable: 0
@ 9624000ns | [UART] raw: '{'h20, 'h20, 'h50, 'h4d, 'h50, 'h45, 'h6e, 'h61, 'h62, 'h6c, 'h65, 'h3a, 'h20, 'h30, 'ha}
@ 12528000ns | [UART] SRAM: 2h banks x 200h words
@ 12528000ns | [UART] raw: '{'h20, 'h20, 'h53, 'h52, 'h41, 'h4d, 'h3a, 'h20, 'h32, 'h68, 'h20, 'h62, 'h61, 'h6e, 'h6b, 'h73, 'h20, 'h78, 'h20, 'h32, 'h30, 'h30, 'h68, 'h20, 'h77, 'h6f, 'h72, 'h64, 'h73, 'ha}
@ 13786400ns | [UART] Peripherals:
@ 13786400ns | [UART] raw: '{'h50, 'h65, 'h72, 'h69, 'h70, 'h68, 'h65, 'h72, 'h61, 'h6c, 'h73, 'h3a, 'ha}
@ 15722400ns | [UART] Debug : present
@ 15722400ns | [UART] raw: '{'h20, 'h20, 'h44, 'h65, 'h62, 'h75, 'h67, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 17658400ns | [UART] Bootrom : present
@ 17658400ns | [UART] raw: '{'h20, 'h20, 'h42, 'h6f, 'h6f, 'h74, 'h72, 'h6f, 'h6d, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 19594400ns | [UART] CLINT : present
@ 19594400ns | [UART] raw: '{'h20, 'h20, 'h43, 'h4c, 'h49, 'h4e, 'h54, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 21530400ns | [UART] SoC Ctrl: present
@ 21530400ns | [UART] raw: '{'h20, 'h20, 'h53, 'h6f, 'h43, 'h20, 'h43, 'h74, 'h72, 'h6c, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 23466400ns | [UART] UART : present
@ 23466400ns | [UART] raw: '{'h20, 'h20, 'h55, 'h41, 'h52, 'h54, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 25402400ns | [UART] GPIO : present
@ 25402400ns | [UART] raw: '{'h20, 'h20, 'h47, 'h50, 'h49, 'h4f, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 27338400ns | [UART] Timer : present
@ 27338400ns | [UART] raw: '{'h20, 'h20, 'h54, 'h69, 'h6d, 'h65, 'h72, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 29661600ns | [UART] iDMA : not present
@ 29661600ns | [UART] raw: '{'h20, 'h20, 'h69, 'h44, 'h4d, 'h41, 'h20, 'h20, 'h20, 'h20, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 31984800ns | [UART] User ROM: not present
@ 31984800ns | [UART] raw: '{'h20, 'h20, 'h55, 'h73, 'h65, 'h72, 'h20, 'h52, 'h4f, 'h4d, 'h3a, 'h20, 'h6e, 'h6f, 'h74, 'h20, 'h70, 'h72, 'h65, 'h73, 'h65, 'h6e, 'h74, 'ha}
@ 32015800ns | [JTAG] Simulation finished: SUCCESS
- ../rtl/test/croc_vip.sv:278: Verilog $finish
- S i m u l a t i o n R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 32ms; walltime 11.396 s; speed 2.810 ms/s
- Verilator: cpu 11.394 s on 1 threads; allocated 6 MB
Hello world simulation passed.
=============================================
Phase 2: iDMA enabled — unit tests
=============================================
[INFO][ENV] Croc root: /fosic/designs/croc
[INFO][ENV] KLayout path: /fosic/designs/croc/ihp13/sg13cmos5l/libs.tech/klayout
[INFO][Bender] Generate croc_netlist_yosys.f
[INFO][Bender] Remove absolute paths
[INFO][Bender] File list generated: croc_netlist_yosys.f
[INFO][Verilator] Build Yosys-netlist simulation
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:67:14: Ignoring unsupported: specify block construct
67 | (A => Y) = 0;
| ^
... For warning description see https://verilator.org/warn/SPECIFYIGN?v=5.052
... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message.
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:85:14: Ignoring unsupported: specify block construct
85 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:103:14: Ignoring unsupported: specify block construct
103 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:121:14: Ignoring unsupported: specify block construct
121 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:142:15: Ignoring unsupported: specify block construct
142 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:164:15: Ignoring unsupported: specify block construct
164 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:183:14: Ignoring unsupported: specify block construct
183 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:202:14: Ignoring unsupported: specify block construct
202 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:221:14: Ignoring unsupported: specify block construct
221 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:241:14: Ignoring unsupported: specify block construct
241 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:297:14: Ignoring unsupported: specify block construct
297 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:332:14: Ignoring unsupported: specify block construct
332 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:367:14: Ignoring unsupported: specify block construct
367 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:397:15: Ignoring unsupported: specify block construct
397 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:445:15: Ignoring unsupported: specify block construct
445 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:491:14: Ignoring unsupported: specify block construct
491 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:526:14: Ignoring unsupported: specify block construct
526 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:567:14: Ignoring unsupported: specify block construct
567 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:610:14: Ignoring unsupported: specify block construct
610 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:653:14: Ignoring unsupported: specify block construct
653 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:694:14: Ignoring unsupported: specify block construct
694 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:733:14: Ignoring unsupported: specify block construct
733 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:765:14: Ignoring unsupported: specify block construct
765 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:798:14: Ignoring unsupported: specify block construct
798 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:831:14: Ignoring unsupported: specify block construct
831 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:870:15: Ignoring unsupported: specify block construct
870 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:946:15: Ignoring unsupported: specify block construct
946 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1022:15: Ignoring unsupported: specify block construct
1022 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1097:15: Ignoring unsupported: specify block construct
1097 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1153:15: Ignoring unsupported: specify block construct
1153 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1209:15: Ignoring unsupported: specify block construct
1209 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1259:15: Ignoring unsupported: specify block construct
1259 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1291:15: Ignoring unsupported: specify block construct
1291 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1326:16: Ignoring unsupported: specify block construct
1326 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1379:16: Ignoring unsupported: specify block construct
1379 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1434:16: Ignoring unsupported: specify block construct
1434 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1489:16: Ignoring unsupported: specify block construct
1489 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1542:16: Ignoring unsupported: specify block construct
1542 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1583:16: Ignoring unsupported: specify block construct
1583 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1625:14: Ignoring unsupported: specify block construct
1625 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1668:14: Ignoring unsupported: specify block construct
1668 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1700:14: Ignoring unsupported: specify block construct
1700 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1717:14: Ignoring unsupported: specify block construct
1717 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1734:14: Ignoring unsupported: specify block construct
1734 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1751:14: Ignoring unsupported: specify block construct
1751 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1768:14: Ignoring unsupported: specify block construct
1768 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1785:14: Ignoring unsupported: specify block construct
1785 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1802:14: Ignoring unsupported: specify block construct
1802 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1819:14: Ignoring unsupported: specify block construct
1819 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1836:14: Ignoring unsupported: specify block construct
1836 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1853:14: Ignoring unsupported: specify block construct
1853 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1870:14: Ignoring unsupported: specify block construct
1870 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1887:14: Ignoring unsupported: specify block construct
1887 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1904:14: Ignoring unsupported: specify block construct
1904 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:1946:34: Ignoring unsupported: specify block construct
1946 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2002:34: Ignoring unsupported: specify block construct
2002 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2058:34: Ignoring unsupported: specify block construct
2058 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2114:34: Ignoring unsupported: specify block construct
2114 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2165:34: Ignoring unsupported: specify block construct
2165 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2210:34: Ignoring unsupported: specify block construct
2210 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2255:34: Ignoring unsupported: specify block construct
2255 | (negedge CK => (ECK+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2374:32: Ignoring unsupported: specify block construct
2374 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2449:28: Ignoring unsupported: specify block construct
2449 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2491:28: Ignoring unsupported: specify block construct
2491 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2533:28: Ignoring unsupported: specify block construct
2533 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2575:28: Ignoring unsupported: specify block construct
2575 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2617:28: Ignoring unsupported: specify block construct
2617 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2659:28: Ignoring unsupported: specify block construct
2659 | (posedge CK => (Q+:D)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2710:32: Ignoring unsupported: specify block construct
2710 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2778:32: Ignoring unsupported: specify block construct
2778 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2846:32: Ignoring unsupported: specify block construct
2846 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2914:32: Ignoring unsupported: specify block construct
2914 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:2994:32: Ignoring unsupported: specify block construct
2994 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3094:32: Ignoring unsupported: specify block construct
3094 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3194:32: Ignoring unsupported: specify block construct
3194 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3294:32: Ignoring unsupported: specify block construct
3294 | (negedge RB => (Q0:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3391:32: Ignoring unsupported: specify block construct
3391 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3456:32: Ignoring unsupported: specify block construct
3456 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3521:32: Ignoring unsupported: specify block construct
3521 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3586:32: Ignoring unsupported: specify block construct
3586 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3651:32: Ignoring unsupported: specify block construct
3651 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3716:32: Ignoring unsupported: specify block construct
3716 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3784:32: Ignoring unsupported: specify block construct
3784 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3860:32: Ignoring unsupported: specify block construct
3860 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:3936:32: Ignoring unsupported: specify block construct
3936 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4012:32: Ignoring unsupported: specify block construct
4012 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4088:32: Ignoring unsupported: specify block construct
4088 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4164:32: Ignoring unsupported: specify block construct
4164 | (negedge RB => (Q+:1'b0)) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4208:14: Ignoring unsupported: specify block construct
4208 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4242:16: Ignoring unsupported: specify block construct
4242 | (A => CO) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4307:15: Ignoring unsupported: specify block construct
4307 | (A => CO) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4333:14: Ignoring unsupported: specify block construct
4333 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4350:14: Ignoring unsupported: specify block construct
4350 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4367:14: Ignoring unsupported: specify block construct
4367 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4384:14: Ignoring unsupported: specify block construct
4384 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4401:14: Ignoring unsupported: specify block construct
4401 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4418:14: Ignoring unsupported: specify block construct
4418 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4435:14: Ignoring unsupported: specify block construct
4435 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4452:14: Ignoring unsupported: specify block construct
4452 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4469:14: Ignoring unsupported: specify block construct
4469 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4486:14: Ignoring unsupported: specify block construct
4486 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4522:14: Ignoring unsupported: specify block construct
4522 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4563:14: Ignoring unsupported: specify block construct
4563 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4604:14: Ignoring unsupported: specify block construct
4604 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4656:14: Ignoring unsupported: specify block construct
4656 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4732:14: Ignoring unsupported: specify block construct
4732 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4808:14: Ignoring unsupported: specify block construct
4808 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4884:14: Ignoring unsupported: specify block construct
4884 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4948:14: Ignoring unsupported: specify block construct
4948 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:4988:14: Ignoring unsupported: specify block construct
4988 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5028:14: Ignoring unsupported: specify block construct
5028 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5079:14: Ignoring unsupported: specify block construct
5079 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5154:14: Ignoring unsupported: specify block construct
5154 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5229:14: Ignoring unsupported: specify block construct
5229 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5304:14: Ignoring unsupported: specify block construct
5304 | (D => Q) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5360:15: Ignoring unsupported: specify block construct
5360 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5400:15: Ignoring unsupported: specify block construct
5400 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5440:15: Ignoring unsupported: specify block construct
5440 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5476:16: Ignoring unsupported: specify block construct
5476 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5511:16: Ignoring unsupported: specify block construct
5511 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5549:15: Ignoring unsupported: specify block construct
5549 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5596:15: Ignoring unsupported: specify block construct
5596 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5643:15: Ignoring unsupported: specify block construct
5643 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5690:15: Ignoring unsupported: specify block construct
5690 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5737:16: Ignoring unsupported: specify block construct
5737 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5775:16: Ignoring unsupported: specify block construct
5775 | (A0 => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5807:15: Ignoring unsupported: specify block construct
5807 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5828:15: Ignoring unsupported: specify block construct
5828 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5849:15: Ignoring unsupported: specify block construct
5849 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5870:15: Ignoring unsupported: specify block construct
5870 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5891:15: Ignoring unsupported: specify block construct
5891 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5913:14: Ignoring unsupported: specify block construct
5913 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5935:14: Ignoring unsupported: specify block construct
5935 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5957:14: Ignoring unsupported: specify block construct
5957 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:5979:14: Ignoring unsupported: specify block construct
5979 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6001:14: Ignoring unsupported: specify block construct
6001 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6023:15: Ignoring unsupported: specify block construct
6023 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6046:15: Ignoring unsupported: specify block construct
6046 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6069:15: Ignoring unsupported: specify block construct
6069 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6093:14: Ignoring unsupported: specify block construct
6093 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6117:14: Ignoring unsupported: specify block construct
6117 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6140:15: Ignoring unsupported: specify block construct
6140 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6164:15: Ignoring unsupported: specify block construct
6164 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6189:15: Ignoring unsupported: specify block construct
6189 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6214:15: Ignoring unsupported: specify block construct
6214 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6241:14: Ignoring unsupported: specify block construct
6241 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6264:15: Ignoring unsupported: specify block construct
6264 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6285:15: Ignoring unsupported: specify block construct
6285 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6307:14: Ignoring unsupported: specify block construct
6307 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6329:14: Ignoring unsupported: specify block construct
6329 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6351:14: Ignoring unsupported: specify block construct
6351 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6373:14: Ignoring unsupported: specify block construct
6373 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6395:15: Ignoring unsupported: specify block construct
6395 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6418:15: Ignoring unsupported: specify block construct
6418 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6441:15: Ignoring unsupported: specify block construct
6441 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6464:15: Ignoring unsupported: specify block construct
6464 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6488:14: Ignoring unsupported: specify block construct
6488 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6512:14: Ignoring unsupported: specify block construct
6512 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6535:15: Ignoring unsupported: specify block construct
6535 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6559:15: Ignoring unsupported: specify block construct
6559 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6584:15: Ignoring unsupported: specify block construct
6584 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6609:15: Ignoring unsupported: specify block construct
6609 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6636:14: Ignoring unsupported: specify block construct
6636 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6663:14: Ignoring unsupported: specify block construct
6663 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6687:14: Ignoring unsupported: specify block construct
6687 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6723:14: Ignoring unsupported: specify block construct
6723 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6759:14: Ignoring unsupported: specify block construct
6759 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6792:14: Ignoring unsupported: specify block construct
6792 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6832:14: Ignoring unsupported: specify block construct
6832 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6871:14: Ignoring unsupported: specify block construct
6871 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6903:14: Ignoring unsupported: specify block construct
6903 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:6940:15: Ignoring unsupported: specify block construct
6940 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7014:15: Ignoring unsupported: specify block construct
7014 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7086:15: Ignoring unsupported: specify block construct
7086 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7139:15: Ignoring unsupported: specify block construct
7139 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7190:16: Ignoring unsupported: specify block construct
7190 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7241:16: Ignoring unsupported: specify block construct
7241 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7292:16: Ignoring unsupported: specify block construct
7292 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7343:16: Ignoring unsupported: specify block construct
7343 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7394:16: Ignoring unsupported: specify block construct
7394 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7433:14: Ignoring unsupported: specify block construct
7433 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7473:14: Ignoring unsupported: specify block construct
7473 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7514:14: Ignoring unsupported: specify block construct
7514 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7559:14: Ignoring unsupported: specify block construct
7559 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7595:14: Ignoring unsupported: specify block construct
7595 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7613:14: Ignoring unsupported: specify block construct
7613 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7631:14: Ignoring unsupported: specify block construct
7631 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7652:15: Ignoring unsupported: specify block construct
7652 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7674:15: Ignoring unsupported: specify block construct
7674 | (AB => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7693:14: Ignoring unsupported: specify block construct
7693 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7712:14: Ignoring unsupported: specify block construct
7712 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7731:14: Ignoring unsupported: specify block construct
7731 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7751:14: Ignoring unsupported: specify block construct
7751 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7771:14: Ignoring unsupported: specify block construct
7771 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7789:14: Ignoring unsupported: specify block construct
7789 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7837:14: Ignoring unsupported: specify block construct
7837 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7855:14: Ignoring unsupported: specify block construct
7855 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7881:15: Ignoring unsupported: specify block construct
7881 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7912:15: Ignoring unsupported: specify block construct
7912 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:7947:15: Ignoring unsupported: specify block construct
7947 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8001:15: Ignoring unsupported: specify block construct
8001 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8051:15: Ignoring unsupported: specify block construct
8051 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8082:15: Ignoring unsupported: specify block construct
8082 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8117:15: Ignoring unsupported: specify block construct
8117 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../ihp13/pdk/verilog/ez130_8t.v:8171:15: Ignoring unsupported: specify block construct
8171 | (A => Y) = 0;
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x32_c2_bm_bist.v:138:54: Ignoring unsupported: specify block construct
138 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-SPECIFYIGN: ../technology/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v:137:54: Ignoring unsupported: specify block construct
137 | (posedge A_CLK *> (A_DOUT : A_DIN)) = (1.0, 1.0);
| ^
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:93576:63: Instance has missing pin: 'busy_o'
93576 | \croc_idma$croc_chip.i_croc_soc.i_croc.gen_dma.i_croc_idma \gen_dma.i_croc_idma (
| ^~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:94781:186: ... Location of port declaration
94781 | module \croc_idma$croc_chip.i_croc_soc.i_croc.gen_dma.i_croc_idma (clk_i, rst_ni, obi_cfg_req_i, obi_cfg_rsp_o, obi_read_req_o, obi_read_rsp_i, obi_write_req_o, obi_write_rsp_i, irq_o, busy_o);
| ^~~~~~
... For warning description see https://verilator.org/warn/PINMISSING?v=5.052
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:93590:70: Instance has missing pin: 'impl_o'
93590 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram \gen_sram_bank[0].i_sram (
| ^~~~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:255227:143: ... Location of port declaration
255227 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:93611:70: Instance has missing pin: 'impl_o'
93611 | \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram \gen_sram_bank[1].i_sram (
| ^~~~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:255288:143: ... Location of port declaration
255288 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:93728:53: Instance has missing pin: 'tdo_oe_o'
93728 | \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag i_dmi_jtag (
| ^~~~~~~~~~
../yosys/out/netlist_debug.v:218208:225: ... Location of port declaration
218208 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o);
| ^~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:94714:55: Instance has missing pin: 'overflow_o'
94714 | \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer i_obi_timer (
| ^~~~~~~~~~~
../yosys/out/netlist_debug.v:233070:108: ... Location of port declaration
233070 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o);
| ^~~~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:94749:49: Instance has missing pin: 'irq_no'
94749 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:237159:142: ... Location of port declaration
237159 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:94749:49: Instance has missing pin: 'rts_no'
94749 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:237159:150: ... Location of port declaration
237159 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:94749:49: Instance has missing pin: 'dtr_no'
94749 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:237159:158: ... Location of port declaration
237159 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:94749:49: Instance has missing pin: 'out1_no'
94749 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:237159:166: ... Location of port declaration
237159 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:94749:49: Instance has missing pin: 'out2_no'
94749 | \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart i_uart (
| ^~~~~~
../yosys/out/netlist_debug.v:237159:175: ... Location of port declaration
237159 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:224156:85: Instance has missing pin: 'src_clear_pending_o'
224156 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req \i_dmi_cdc.i_cdc_req (
| ^~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:2409:259: ... Location of port declaration
2409 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:224174:86: Instance has missing pin: 'dst_clear_pending_o'
224174 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp (
| ^~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:2699:201: ... Location of port declaration
2699 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../yosys/out/netlist_debug.v:224174:86: Instance has missing pin: 'src_clear_pending_o'
224174 | \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp \i_dmi_cdc.i_cdc_resp (
| ^~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:2699:260: ... Location of port declaration
2699 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_verification/clk_rst_gen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module clk_rst_gen #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.052
... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message.
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
56 | module tc_sram #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_sram_impl.sv:27:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
27 | module tc_sram_impl #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module tc_clk_and2 (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
21 | module tc_clk_buffer (
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
31 | module tc_clk_gating #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:56:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
56 | module tc_clk_inverter (
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:75:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
75 | module tc_clk_mux2 (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:86:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
86 | module tc_clk_xor2 (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:96:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
96 | module tc_clk_or2 (
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/tech_cells_generic/tc_clk.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
107 | module tc_clk_delay #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/binary_to_gray.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module binary_to_gray #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter_pkg.sv:14:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | package cb_filter_pkg;
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cc_onehot.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module cc_onehot #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | package cdc_reset_ctrlr_pkg;
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cf_math_pkg.sv:18:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | package cf_math_pkg;
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div.sv:70:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
70 | module clk_int_div #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/credit_counter.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module credit_counter #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/delta_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module delta_counter #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | package ecc_pkg;
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/edge_propagator_tx.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module edge_propagator_tx (
| ^~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/exp_backoff.sv:25:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
25 | module exp_backoff #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/fifo_v3.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module fifo_v3 #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/gray_to_binary.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module gray_to_binary #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/heaviside.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module heaviside #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_4phase_handshake.sv:44:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
44 | module isochronous_4phase_handshake (
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/isochronous_spill_register.sv:41:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
41 | module isochronous_spill_register #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
24 | module lfsr #(
| ^~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_16bit.sv:23:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
23 | module lfsr_16bit #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lfsr_8bit.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module lfsr_8bit #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lossy_valid_to_stream.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
49 | module lossy_valid_to_stream #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/mv_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module mv_filter #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/onehot_to_bin.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module onehot_to_bin #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/plru_tree.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module plru_tree #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/passthrough_stream_fifo.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module passthrough_stream_fifo #(
| ^~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/popcount.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
22 | module popcount #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ring_buffer.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
22 | module ring_buffer #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/rr_arb_tree.sv:49:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
49 | module rr_arb_tree #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen_bypass.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module rstgen_bypass #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/serial_deglitch.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module serial_deglitch #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module shift_reg #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/shift_reg_gated.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module shift_reg_gated #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register_flushable.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module spill_register_flushable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_demux.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module stream_demux #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_filter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module stream_filter (
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
21 | module stream_fork #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join_dynamic.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module stream_join_dynamic #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_mux.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_mux #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_throttle.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module stream_throttle #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/sub_per_hash.sv:39:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
39 | module sub_per_hash #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/sync.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module sync #(
| ^~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/sync_wedge.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module sync_wedge #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/unread.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module unread (
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module read #(
| ^~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_dync.sv:40:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
40 | module addr_decode_dync #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/boxcar.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module boxcar #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:43:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
43 | module cdc_2phase #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
92 | module cdc_2phase_src #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase.sv:142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
142 | module cdc_2phase_dst #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:36:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
36 | module cdc_4phase #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:92:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
92 | module cdc_4phase_src #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_4phase.sv:205:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
205 | module cdc_4phase_dst #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_int_div_static.sv:60:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
60 | module clk_int_div_static #(
| ^~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/trip_counter.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module trip_counter #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode.sv:35:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
35 | module addr_decode #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/addr_decode_napot.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module addr_decode_napot #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/multiaddr_decode.sv:32:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
32 | module multiaddr_decode #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:45:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
45 | module cb_filter #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cb_filter.sv:203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
203 | module hash_block #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_2phase.sv:47:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
47 | module cdc_fifo_2phase #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
73 | module clk_mux_glitch_free #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/clk_mux_glitch_free.sv:256:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
256 | module clk_or_tree #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/counter.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module counter #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_decode.sv:29:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
29 | module ecc_decode import ecc_pkg::*; #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/ecc_encode.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
22 | module ecc_encode import ecc_pkg::*; #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/edge_detect.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module edge_detect (
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/lzc.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module lzc #(
| ^~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/max_counter.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module max_counter #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/rstgen.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module rstgen (
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/spill_register.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module spill_register #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_delay.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module stream_delay #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module stream_fifo #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fork_dynamic.sv:24:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
24 | module stream_fork_dynamic #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_join.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module stream_join #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
109 | module cdc_reset_ctrlr
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_reset_ctrlr.sv:187:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
187 | module cdc_reset_ctrlr_half
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
103 | module cdc_fifo_gray #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:171:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
171 | module cdc_fifo_gray_src #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray.sv:231:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
231 | module cdc_fifo_gray_dst #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/fall_through_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module fall_through_register #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/id_queue.sv:50:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
50 | module id_queue #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_to_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module stream_to_mem #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter_flushable.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_arbiter_flushable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_fifo_optimal_wrap.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module stream_fifo_optimal_wrap #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_register.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_register #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_xbar.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module stream_xbar #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
103 | module cdc_fifo_gray_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
268 | module cdc_fifo_gray_src_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_fifo_gray_clearable.sv:328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
328 | module cdc_fifo_gray_dst_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:54:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
54 | module cdc_2phase_clearable #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
199 | module cdc_2phase_src_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/cdc_2phase_clearable.sv:269:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
269 | module cdc_2phase_dst_clearable #(
| ^~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks_detailed.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module mem_to_banks_detailed #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_arbiter.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module stream_arbiter #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/stream_omega_net.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module stream_omega_net #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/common_cells/mem_to_banks.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module mem_to_banks #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_pkg.sv:7:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | package obi_pkg;
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_rready_converter.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_rready_converter #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/apb_to_obi.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module apb_to_obi #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_to_apb.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module obi_to_apb #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_atop_resolver
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_atop_resolver.sv:536:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
536 | module obi_atop_resolver_intf
| ^~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_cut.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_cut #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_demux #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_demux.sv:114:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
114 | module obi_demux_intf #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_err_sbr #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_err_sbr.sv:69:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
69 | module obi_err_sbr_intf #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module obi_mux #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_mux.sv:166:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
166 | module obi_mux_intf #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_sram_shim.sv:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
7 | module obi_sram_shim #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:8:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | module obi_xbar #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi/obi_xbar.sv:161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
161 | module obi_xbar_intf #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/apb/apb_pkg.sv:15:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | package apb_pkg;
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | package cve2_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_alu.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module cve2_alu #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_branch_predict.sv:21:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
21 | module cve2_branch_predict (
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_compressed_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module cve2_compressed_decoder (
| ^~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_controller.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module cve2_controller #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_counter.sv:6:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
6 | module cve2_counter #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_csr.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module cve2_csr #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_decoder.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module cve2_decoder #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_fetch_fifo.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_fetch_fifo #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_load_store_unit.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module cve2_load_store_unit
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_fast.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module cve2_multdiv_fast #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_multdiv_slow.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module cve2_multdiv_slow
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_pmp.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module cve2_pmp #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_register_file_ff.sv:14:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14 | module cve2_register_file_ff #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_wb.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module cve2_wb #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_cs_registers.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_cs_registers #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_ex_block.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module cve2_ex_block #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_id_stage.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module cve2_id_stage #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_prefetch_buffer.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module cve2_prefetch_buffer #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_if_stage.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_if_stage import cve2_pkg::*; (
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/cve2/cve2_core.sv:16:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
16 | module cve2_core import cve2_pkg::*; #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_pkg.sv:11:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | package idma_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_channel_coupler.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module idma_channel_coupler #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_dataflow_element.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module idma_dataflow_element #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_read.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module idma_obi_read #(
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_obi_write.sv:10:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | module idma_obi_write #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module idma_nd_midend #(
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_nd_midend.sv:252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
252 | module idma_nd_counter #(
| ^~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_transfer_id_gen.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module idma_transfer_id_gen #(
| ^~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_page_splitter.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module idma_legalizer_page_splitter #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_transport_layer_rw_obi.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13 | module idma_transport_layer_rw_obi #(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_legalizer_rw_obi.sv:15:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
15 | module idma_legalizer_rw_obi #(
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/idma_backend_rw_obi.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module idma_backend_rw_obi #(
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/idma/croc_idma.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module croc_idma #(
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | package obi_uart_pkg;
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_baudgen.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_uart_baudgen import obi_uart_pkg::*; #()
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_interrupts.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_uart_interrupts import obi_uart_pkg::*; #()
| ^~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_modem.sv:12:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | module obi_uart_modem import obi_uart_pkg::*; #()
| ^~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_rx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart_rx import obi_uart_pkg::*; #()
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_tx.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart_tx #()
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart_register.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart_register import obi_uart_pkg::*; #(
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_uart/obi_uart.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module obi_uart #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_pkg.sv:19:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | package dm;
| ^~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module debug_rom (
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv:17:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
17 | module debug_rom_one_scratch (
| ^~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_csrs.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module dm_csrs #(
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_mem.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dm_mem #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_cdc.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dmi_cdc (
| ^~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag_tap.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dmi_jtag_tap #(
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_sba.sv:18:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
18 | module dm_sba #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_top.sv:20:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
20 | module dm_top #(
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dmi_jtag.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19 | module dmi_jtag #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/dm_obi_top.sv:63:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
63 | module dm_obi_top #(
| ^~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module jtag_driver_simple #(
| ^~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/riscv-dbg/tb/jtag_test_simple.sv:163:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
163 | module riscv_dbg_simple #(
| ^~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/croc_pkg.sv:12:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12 | package croc_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/user_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | package user_pkg;
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/soc_ctrl/soc_ctrl_regs_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | package soc_ctrl_regs_pkg;
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/gpio/gpio_reg_pkg.sv:10:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10 | package gpio_reg_pkg;
| ^~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/clint/clint_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | package clint_reg_pkg;
| ^~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/obi_timer/obi_timer_reg_pkg.sv:8:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8 | package obi_timer_reg_pkg;
| ^~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:4:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
4 | module \bootrom$croc_chip.i_croc_soc.i_croc.i_bootrom (clk_i, rst_ni, obi_req_i, obi_rsp_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2409:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
2409 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
2699 | module \cdc_2phase_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp (src_rst_ni, src_clk_i, src_clear_i, src_data_i, src_valid_i, src_ready_o, dst_rst_ni, dst_clk_i, dst_clear_i, dst_clear_pending_o, dst_data_o, dst_valid_o, dst_ready_i, src_clear_pending_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:2968:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
2968 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst (clk_i, rst_ni, data_o, valid_o, ready_i, clear_i, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:5852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
5852 | module \cdc_2phase_dst_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst (clk_i, rst_ni, data_o, valid_o, ready_i, clear_i, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:8262:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
8262 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src (clk_i, rst_ni, data_i, valid_i, ready_o, clear_i, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:9425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9425 | module \cdc_2phase_src_clearable$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src (clk_i, rst_ni, data_i, valid_i, ready_o, clear_i, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10408:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10408 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10536:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10536 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10664:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10664 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10792:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10792 | module \cdc_4phase_dst$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst (clk_i, rst_ni, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:10920:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
10920 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11118 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11316:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11316 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11514 | module \cdc_4phase_src$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src (clk_i, rst_ni, data_i, valid_i, ready_o, async_req_o, async_ack_i, async_data_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11712:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11712 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11820 | module \cdc_reset_ctrlr$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr (a_clk_i, a_rst_ni, a_clear_i, a_clear_o, a_clear_ack_i, a_isolate_o, a_isolate_ack_i, b_clk_i, b_rst_ni, b_clear_i, b_clear_o, b_clear_ack_i, b_isolate_o, b_isolate_ack_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:11928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11928 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:12476:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
12476 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:13024:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13024 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:13572:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
13572 | module \cdc_reset_ctrlr_half$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b (clk_i, rst_ni, clear_i, async_req_o, async_ack_i, async_req_i, async_ack_o, isolate_o, isolate_ack_i, clear_o, clear_ack_i, async_next_phase_o, async_next_phase_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:14120:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
14120 | module \clint$croc_chip.i_croc_soc.i_croc.i_clint (clk_i, rst_ni, obi_req_i, obi_rsp_o, rtc_i, software_irq_o, timer_irq_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:19622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
19622 | module \core_wrap$croc_chip.i_croc_soc.i_croc.i_core_wrap (clk_i, rst_ni, core_busy_o, test_enable_i, irqs_i, timer_irq_i, software_irq_i, boot_addr_i, instr_req_o, instr_gnt_i, instr_rvalid_i, instr_addr_o, instr_rdata_i, instr_err_i, data_req_o, data_gnt_i, data_rvalid_i, data_we_o, data_be_o, data_addr_o, data_wdata_o
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:53375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
53375 | module croc_chip(clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio0_io, gpio1_io, gpio2_io, gpio3_io, gpio4_io, gpio5_io, gpio6_io, gpio7_io, gpio8_io
| ^~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:54205:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
54205 | module \croc_domain$croc_chip.i_croc_soc.i_croc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, user_sbr_obi_req_o, user_sbr_obi_rsp_i, user_mgr_obi_req_i, user_mgr_obi_rsp_o, interrupts_i, core_busy_o
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:94781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
94781 | module \croc_idma$croc_chip.i_croc_soc.i_croc.gen_dma.i_croc_idma (clk_i, rst_ni, obi_cfg_req_i, obi_cfg_rsp_o, obi_read_req_o, obi_read_rsp_i, obi_write_req_o, obi_write_rsp_i, irq_o, busy_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:136630:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
136630 | module \croc_soc$croc_chip.i_croc_soc (clk_i, rst_ni, ref_clk_i, jtag_tck_i, jtag_trst_ni, jtag_tms_i, jtag_tdi_i, jtag_tdo_o, uart_rx_i, uart_tx_o, testmode_i, status_o, gpio_i, gpio_o, gpio_out_en_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:137309:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
137309 | module \cve2_cs_registers$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.cs_registers_i (clk_i, rst_ni, boot_addr_i, hart_id_i, irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_pending_o, pc_id_i, priv_mode_id_o, priv_mode_lsu_o, csr_mstatus_tw_o, csr_mtvec_o, csr_mtvec_init_i, csr_access_i, csr_addr_i, csr_wdata_i, csr_op_i, csr_op_en_i, csr_rdata_o
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:158555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
158555 | module \cve2_register_file_ff$croc_chip.i_croc_soc.i_croc.i_core_wrap.i_core.register_file_i (clk_i, rst_ni, test_en_i, raddr_a_i, rdata_a_o, raddr_b_i, rdata_b_o, waddr_a_i, wdata_a_i, we_a_i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:188604:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
188604 | module \dm_top$croc_chip.i_croc_soc.i_croc.i_dm_top.i_dm_top (clk_i, rst_ni, testmode_i, debug_req_o, unavailable_i, hartinfo_i, slave_req_i, slave_we_i, slave_addr_i, slave_be_i, slave_wdata_i, slave_rdata_o, master_req_o, master_we_o, master_wdata_o, master_be_o, master_gnt_i, dmi_rst_ni, dmi_req_valid_i, dmi_req_ready_o, dmi_req_i
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:218208:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
218208 | module \dmi_jtag$croc_chip.i_croc_soc.i_croc.i_dmi_jtag (clk_i, rst_ni, testmode_i, dmi_rst_no, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, tck_i, tms_i, trst_ni, td_i, td_o, tdo_oe_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:224585:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
224585 | module \gpio$croc_chip.i_croc_soc.i_croc.i_gpio (clk_i, rst_ni, gpio_i, gpio_o, gpio_out_en_o, gpio_in_sync_o, obi_req_i, obi_rsp_o, interrupt_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:233070:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
233070 | module \obi_timer$croc_chip.i_croc_soc.i_croc.i_obi_timer (clk_i, rst_ni, obi_req_i, obi_rsp_o, expired_o, overflow_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:237159:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
237159 | module \obi_uart$croc_chip.i_croc_soc.i_croc.i_uart (clk_i, rst_ni, irq_o, obi_req_i, obi_rsp_o, rxd_i, txd_o, cts_ni, dsr_ni, ri_ni, cd_ni, irq_no, rts_no, dtr_no, out1_no, out2_no);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:251086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
251086 | module \soc_ctrl_regs$croc_chip.i_croc_soc.i_croc.i_soc_ctrl (clk_i, rst_ni, obi_req_i, obi_rsp_o, fetch_en_o, sram_dly_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253116:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253116 | module \sync$croc_chip.i_croc_soc.i_croc.i_clint.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253155 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253194 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253233:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253233 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253272:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253272 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253311:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253311 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253361:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253361 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_req.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253411 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253450:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253450 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_a.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253489:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253489 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253528:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253528 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_cdc_reset_ctrlr.i_cdc_reset_ctrlr_half_b.i_state_transition_cdc_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253567:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253567 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_dst.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253617:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253617 | module \sync$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_cdc.i_cdc_resp.i_src.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253667 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[0].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253706:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253706 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[10].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253745:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253745 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[11].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253784:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253784 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[12].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253823:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253823 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[13].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253862:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253862 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[14].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253901 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[15].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253940:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253940 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[16].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:253979:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
253979 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[17].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254018:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254018 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[18].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254057:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254057 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[19].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254096:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254096 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[1].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254135:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254135 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[20].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254174:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254174 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[21].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254213:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254213 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[22].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254252 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[23].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254291:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254291 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[24].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254330 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[25].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254369:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254369 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[26].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254408:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254408 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[27].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254447:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254447 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[28].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254486:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254486 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[29].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254525:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254525 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[2].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254564:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254564 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[30].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254603:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254603 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[31].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254642 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[3].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254681:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254681 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[4].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254720:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254720 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[5].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254759:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254759 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[6].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254798:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254798 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[7].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254837:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254837 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[8].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254876 | module \sync$croc_chip.i_croc_soc.i_croc.i_gpio.gen_gpios[9].i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254915:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254915 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cd (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254954:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254954 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_cts (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:254993:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
254993 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_dsr (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255032:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255032 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_modem.i_sync_ri (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255071:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255071 | module \sync$croc_chip.i_croc_soc.i_croc.i_uart.i_uart_rx.i_sync (clk_i, rst_ni, serial_i, serial_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255110:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255110 | module \tc_clk_inverter$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_tck_inv (clk_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255127:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255127 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_croc.i_dmi_jtag.i_dmi_jtag_tap.i_dft_tck_mux (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255152:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255152 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_init_no (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255177:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255177 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_n (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255202 | module \tc_clk_mux2$croc_chip.i_croc_soc.i_rstgen.i_rstgen_bypass.i_tc_clk_mux2_rst_no (clk0_i, clk1_i, clk_sel_i, clk_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255227:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255227 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[0].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255288 | module \tc_sram_impl$croc_chip.i_croc_soc.i_croc.gen_sram_bank[1].i_sram (clk_i, rst_ni, impl_i, req_i, we_i, addr_i, wdata_i, be_i, rdata_o, impl_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../yosys/out/netlist_debug.v:255349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
255349 | module \user_domain$croc_chip.i_croc_soc.i_user (clk_i, rst_ni, ref_clk_i, testmode_i, user_sbr_obi_req_i, user_sbr_obi_rsp_o, user_mgr_obi_req_o, user_mgr_obi_rsp_i, gpio_in_sync_i, interrupts_o);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/test/tb_croc_pkg.sv:9:9: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | package tb_croc_pkg;
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/test/croc_vip.sv:9:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
9 | module croc_vip #(
| ^~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-TIMESCALEMOD: ../rtl/test/tb_croc_soc.sv:11:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)
11 | module tb_croc_soc #(
| ^~~~~~~~~~~
../ihp13/pdk/verilog/ez130_8t.v:58:8: ... Location of module with timescale
58 | module AND2X1 (Y, A, B);
| ^~~~~~
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:5975:15: Signal unoptimizable: Circular combinational logic: '__VdfgRegularize_h6e95ff9d_0_546'
5975 | or (Y, A__bar, B__bar);
| ^
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.052
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
../ihp13/pdk/verilog/ez130_8t.v:5975:15: Example path: __VdfgRegularize_h6e95ff9d_0_546
../yosys/out/netlist_debug.v:136626:56: Example path: ASSIGNW
../yosys/out/netlist_debug.v:94801:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o
../ihp13/pdk/verilog/ez130_8t.v:363:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55971:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n3814
../ihp13/pdk/verilog/ez130_8t.v:827:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55107:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2800
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:62224:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D'
62224 | wire \i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D ;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:62221:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_2__reg_D'
62221 | wire \i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_2__reg_D ;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:62221:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_2__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:55101:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2794'
55101 | wire \$abc$203447$new_n2794 ;
| ^~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:55101:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2794
../ihp13/pdk/verilog/ez130_8t.v:363:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55971:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n3814
../ihp13/pdk/verilog/ez130_8t.v:827:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55107:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2800
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:1248:15: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204242.C__bar'
1248 | wire B__bar, C__bar, int_fwire_0;
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:1248:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204242.C__bar
../ihp13/pdk/verilog/ez130_8t.v:4329:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54749:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2433
../yosys/out/netlist_debug.v:54788:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54788:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2474
../ihp13/pdk/verilog/ez130_8t.v:827:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:56133:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n4014
../ihp13/pdk/verilog/ez130_8t.v:5730:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5724:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$208570.A0__bar
../yosys/out/netlist_debug.v:59131:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:59131:8: Example path: __VdfgRegularize_h6e95ff9d_0_600
../yosys/out/netlist_debug.v:251082:47: Example path: ASSIGNW
../yosys/out/netlist_debug.v:237173:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__i_uart__obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:293:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54396:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2075
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:6089:23: Signal unoptimizable: Circular combinational logic: '__VdfgRegularize_h6e95ff9d_0_309'
6089 | or (Y, A__bar, B__bar, C__bar);
| ^
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:6084:7: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$206329.A__bar'
6084 | wire A__bar, B__bar, C__bar;
| ^~~~~~
../ihp13/pdk/verilog/ez130_8t.v:6084:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$206329.A__bar
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:61065:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.core_instr_obi_req_68_'
61065 | wire core_instr_obi_req_68_;
| ^~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:61065:8: Example path: tb_croc_soc.i_croc_soc.i_croc.core_instr_obi_req_68_
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:61067:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.core_instr_obi_req_69_'
61067 | wire core_instr_obi_req_69_;
| ^~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:61067:8: Example path: tb_croc_soc.i_croc_soc.i_croc.core_instr_obi_req_69_
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../yosys/out/netlist_debug.v:54396:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2075'
54396 | wire \$abc$203447$new_n2075 ;
| ^~~~~~~~~~~~~~~~~~~~~~
../yosys/out/netlist_debug.v:54396:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2075
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:6508:16: Signal unoptimizable: Circular combinational logic: '__VdfgRegularize_h6e95ff9d_0_616'
6508 | and (Y, A__bar, B__bar, C__bar);
| ^
../ihp13/pdk/verilog/ez130_8t.v:6508:16: Example path: __VdfgRegularize_h6e95ff9d_0_616
../ihp13/pdk/verilog/ez130_8t.v:727:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:722:7: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$208658.A__bar
../ihp13/pdk/verilog/ez130_8t.v:794:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55822:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n3630
../ihp13/pdk/verilog/ez130_8t.v:198:14: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:198:14: Example path: __VdfgRegularize_h6e95ff9d_0_251
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
%Warning-UNOPTFLAT: ../ihp13/pdk/verilog/ez130_8t.v:60:8: Signal unoptimizable: Circular combinational logic: 'tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.__Vcellinp__$abc$208793$auto$blifparse.cc:397:parse_blif$209840__A'
60 | input A, B;
| ^
../ihp13/pdk/verilog/ez130_8t.v:60:8: Example path: tb_croc_soc.i_croc_soc.i_croc.gen_dma.i_croc_idma.__Vcellinp__$abc$208793$auto$blifparse.cc:397:parse_blif$209840__A
../yosys/out/netlist_debug.v:107954:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:94801:17: Example path: tb_croc_soc.i_croc_soc.i_croc.__Vcellout__gen_dma.i_croc_idma__obi_write_req_o
../ihp13/pdk/verilog/ez130_8t.v:363:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55971:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n3814
../ihp13/pdk/verilog/ez130_8t.v:827:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55107:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2800
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255400:8: Example path: tb_croc_soc.i_croc_soc.i_user.$abc$226127$new_n114
../yosys/out/netlist_debug.v:255948:64: Example path: ASSIGNW
../yosys/out/netlist_debug.v:255366:17: Example path: tb_croc_soc.i_croc_soc.__Vcellout__i_user__user_sbr_obi_rsp_o
../ihp13/pdk/verilog/ez130_8t.v:5909:5: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54535:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2216
../ihp13/pdk/verilog/ez130_8t.v:789:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:786:23: Example path: tb_croc_soc.i_croc_soc.i_croc.i_core_wrap.$abc$199151$auto$blifparse.cc:397:parse_blif$201579.C__bar
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6866:26: Example path: __VdfgRegularize_h6e95ff9d_0_2190
../yosys/out/netlist_debug.v:54661:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:54661:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2344
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:793:26: Example path: __VdfgRegularize_h6e95ff9d_0_2304
../ihp13/pdk/verilog/ez130_8t.v:6484:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55071:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2763
../ihp13/pdk/verilog/ez130_8t.v:5907:6: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:5905:15: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$auto$blifparse.cc:397:parse_blif$204156.B__bar
../yosys/out/netlist_debug.v:62224:8: Example path: ASSIGNW
../yosys/out/netlist_debug.v:62224:8: Example path: tb_croc_soc.i_croc_soc.i_croc.i_main_xbar.gen_mux[2].i_mux.i_rr_arb.gen_arbiter.gen_int_rr.gen_lock.req_q_3__reg_D
../ihp13/pdk/verilog/ez130_8t.v:63:6: Example path: ASSIGNW
../yosys/out/netlist_debug.v:55076:8: Example path: tb_croc_soc.i_croc_soc.i_croc.$abc$203447$new_n2769
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: ASSIGNW
../ihp13/pdk/verilog/ez130_8t.v:6089:23: Example path: __VdfgRegularize_h6e95ff9d_0_309
../ihp13/pdk/verilog/ez130_8t.v:6605:6: Example path: ASSIGNW
make: Entering directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys'
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /foss/tools/verilator/share/verilator/include/verilated.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_dpi.o /foss/tools/verilator/share/verilator/include/verilated_dpi.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /foss/tools/verilator/share/verilator/include/verilated_timing.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /foss/tools/verilator/share/verilator/include/verilated_threads.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.fast.gch
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -x c++-header Vtb_croc_soc__pch.h -o Vtb_croc_soc__pch.h.slow.gch
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc__ConstPool__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__0__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__1__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__2__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__3__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc___024root__4__Slow.cpp
ccache g++ -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.slow -c Vtb_croc_soc__Syms__Slow.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_0.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_1.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_2.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc_vm_classes_3.cpp
ccache g++ -Os -I. -MMD -I/foss/tools/verilator/share/verilator/include -I/foss/tools/verilator/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_croc_soc__pch.h.fast -c Vtb_croc_soc__Dpi.cpp
g++ -fuse-ld=mold verilated.o verilated_dpi.o verilated_timing.o verilated_threads.o Vtb_croc_soc__ALL.a -pthread -lpthread -latomic -o Vtb_croc_soc
rm Vtb_croc_soc__ALL.verilator_deplist.tmp
make: Leaving directory '/fosic/designs/croc/verilator/obj_dir_netlist_yosys'
- V e r i l a t i o n R e p o r t: Verilator 5.052 2026-09-05 rev v5.052
- Verilator: Built from 218.126 MB sources in 529 modules, into 33.489 MB in 30 C++ files needing 0.039 MB
- Verilator: Walltime 79.367 s (elab=1.407, cvt=13.009, bld=63.184); cpu 16.617 s on 4 threads; allocated 1105.473 MB
Found 8 test(s) to run
=========================================
Running test_clint ... PASS
Running test_compute ... PASS
Running test_gpio ... PASS
Running test_idma ... PASS
Running test_interrupts ... PASS
Running test_obi_timer ... PASS
Running test_soc_ctrl ... PASS
Running test_uart ... PASS
=========================================
Summary: 8 passed, 0 failed, 8 total
All tests passed.
=============================================
Simulation completed
=============================================